System and method for disabling schematics

• US 6,675,366 B1
• Filed: 02/25/2003
• Issued: 01/06/2004
• Est. Priority Date: 07/26/2001
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nolan, Stephen David
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THAO P
• Application Number:
  US10/375,831
• Time in Patent Office: 315 Days
• Field of Search: 716/11-18
• US Class Current: 716/102
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

A system and method for designing schematic diagrams of electronic circuits is provided. A library of electronic components represented in graphical form are selectable by a user for inclusion into a schematic diagram. The components are connected together to define a circuit that performs a function. In order to simulate and test a particular portion of the circuit rather than the entire circuit, the present invention provides a disabling routine that disables portions of the circuit not to be included in the simulation. The present invention allows a circuit designer/tester to focus on desired areas of a circuit while ignoring others.

Claims

1. A system for designing a schematic diagram of an electronic circuit where a textual description is generated. representing the schematic diagram, the textual description being inputted to a circuit simulation program that simulates the electronic circuit of the schematic diagram, the system comprising:

a schematic editor for connecting electronic components based on user instructions, the connected electronic components forming a schematic diagram; and

a hiding mechanism for hiding a selected sub-circuit of the schematic diagram such that when a textual description is generated representing the schematic diagram, the selected sub-circuit being represented as a different sub-circuit.

2. The system for designing a schematic diagram as set forth in claim 1 wherein the hiding mechanism includes logic for assigning at least one of dummy values and dummy components to replace the selected sub-circuit.

3. The system for designing a schematic diagram as set forth in claim 1 wherein the hiding mechanism maintains the selected sub-circuit in the schematic diagram.