Technique for suppression of edge current in semiconductor devices

• US 6,677,182 B2
• Filed: 04/20/2001
• Issued: 01/13/2004
• Est. Priority Date: 04/20/2000
• Status: Expired due to Fees

• Current Assignee: Digirad Corporation
• Original Assignee: Digirad Corporation
• Inventors: Carlson, Lars S.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Luu, Chuong A
• Application Number:
  US09/839,874
• Publication Number:
  US 20010034105A1
• Time in Patent Office: 998 Days
• Field of Search: 438/68, 438/73, 438/113, 438/460
• US Class Current: 438/113
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 31/1121 Devices with Schottky gate
• CPC Class Codes: H01L 31/186 Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.

Claims

1. A method comprising:

forming a semiconductor device on a substrate;

dicing the semiconductor device to a desired size to form a diced semiconductor device, with diced edge portions formed by said dicing; and

after said dicing, coating at least a portion of at least one of said diced edge portions of the semiconductor device with a metal or intermetallic layer to form a Schottky barrier at an interface between semiconductor material on said at least one of said diced edge portions and said metal layer; and

using said Schottky barrier to generate a depletion region within the substrate.

2. The method of claim 1, wherein said coating comprises covering the diced edge using displacement plating.

3. The method of claim 1, wherein said coating comprising covering the diced edge using autocatalytic electroless deposition.

4. A method as in claim 1, further comprising:

etching the diced edge prior to coating with the metal layer.

5. The method of claim 1, further comprising sealing the diced edge against contamination and environmental effects by coating the entire edge with the metal layer.

6. The method of claim 1, further comprising reducing the series resistance of an indirect front-to-back contact by coating all of at least one diced edge with the metal layer.

7. A method comprising:

forming a photodiode array on a substrate;

dicing the photodiode array to a desired size to form a diced semiconductor device, with diced edge portions formed by dicing;

after said dicing, coating at least a portion of a diced edge of the photodiode array with a metal or intermetallic layer to form a Schottky barrier at an interface between semiconductor material on at least one of said diced edge portions and said metal layer; and

using the Schottky barrier to suppress injection of edge generation current into the photodiode array.

8. A method as in claim 7, wherein said coating comprises covering the diced edge using displacement plating.

9. A method of claim 7, wherein said coating comprises covering the diced edge using autocatalytic electroless deposition.