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Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure

  • US 6,677,612 B2
  • Filed: 08/28/2001
  • Issued: 01/13/2004
  • Est. Priority Date: 07/28/1997
  • Status: Expired due to Fees
First Claim
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1. A MOS structure, comprising:

  • two first activated areas of a first field effect transistor, said two first activated areas having a first conductivity type and being laterally spaced apart from one another;

    two second activated areas of a second field effect transistor adjacent said first field effect transistor, said two second activated areas having a second conductivity type opposite said first conductivity type;

    an isolation barrier comprising dielectric material and disposed between a first activated area and a second activated area, said isolation barrier having at most the same height as at least said second activated area; and

    an interconnect comprising conductive material, said interconnect including at least one downwardly extending member to communicate with said first activated area and said second activated area.

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