Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

• US 6,677,637 B2
• Filed: 06/11/1999
• Issued: 01/13/2004
• Est. Priority Date: 06/11/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ning, Tak H., Cote, William J., Bernstein, Kerry, Bracchitta, John A., Pricer, Wilbur D.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US09/330,803
• Publication Number:
  US 20020081832A1
• Time in Patent Office: 1,677 Days
• Field of Search: 257/307, 257/308, 257/535
• US Class Current: 257/307
• CPC Class Codes: H01G 4/1272 Semiconductive ceramic capacitors
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Claims

1. A decoupling capacitor for a semiconductor device, said capacitor comprising:

a first dielectric insulator layer,

a low resistance conductor comprising at least two interdigitized patterns on a surface of the first dielectric insulator layer, each of said two interdigitized patterns being adjacent to the other such that their sidewalls form plates of said capacitor,

a dielectric material provided between said at least two interdigitized patterns, said dielectric material having a lower portion which is adjacent to said surface of said first dielectric insulator layer and an upper surface which is coplanar with an upper surface of said at least two interdigitized patterns, and

a second dielectric insulator layer provided on said dielectric material and said interdigitized patterns,

wherein said first dielectric insulator layer and said second dielectric insulator layer each have dielectric constants that are lower than a dielectric constant of said dielectric material.

2. The decoupling capacitor of claim 1, wherein said dielectric material comprises tantalum pentoxide.

3. The decoupling capacitor of claim 1, wherein said dielectric material comprises silicon nitride.

4. The decoupling capacitor of claim 1, further comprising a polish stop provided on each of said two interdigitized patterns.

5. The decoupling capacitor of claim 4, wherein said polish stop comprises diamond-like carbon.

6. The decoupling capacitor of claim 4, wherein said polish stop is non-conformally deposited on said interdigitized patterns.

7. The decoupling capacitor of claim 4, wherein said polish stop comprises silicon nitride.

8. The decoupling capacitor of claim 1, wherein said dielectric insulator layer comprises fluorinated glass.

16. The decoupling capacitor of claim 1, wherein the decoupling capacitor is configured such that a first wiring plane comprises the first dielectric insulator layer and the dielectric material.

17. The decoupling capacitor of claim 1, wherein said interdigitized pattern comprises a comb-shaped pattern.

9. A capacitor for a semiconductor device, said capacitor comprising:

a first dielectric layer;

a plurality of interdigitized metal wires provided on said first dielectric layer;

dielectric material provided between said plurality of interdigitized metal wires; and

a second dielectric layer provided on said dielectric material and said plurality of interdigitized metal wires,

wherein said first and second dielectric layers each have dielectric constants that are lower than a dielectric constant of said dielectric material.

10. The capacitor of claim 9, wherein said dielectric material comprises tantalum pentoxide.

11. The capacitor of claim 9, wherein said dielectric material comprises silicon nitride.

12. The capacitor of claim 9, further comprising a polish stop provided on each of the plurality of interdigitized metal wires.

13. The capacitor of claim 12, wherein said polish stop comprises diamond-like carbon.

14. The capacitor of claim 12, wherein said polish stop is non-conformally deposited on said plurality of interdigitized metal wires.

15. The capacitor of claim 12, wherein said polish stop comprises silicon nitride.

18. The capacitor of claim 9, wherein the decoupling capacitor is configured such that a first wiring plane comprises the first dielectric insulator layer and the dielectric material.

19. The capacitor of claim 9, wherein said interdigitized pattern comprises a comb-shaped pattern.