Semiconductor structure with improved smaller forward voltage loss and higher blocking capability

• US 6,677,641 B2
• Filed: 10/17/2001
• Issued: 01/13/2004
• Est. Priority Date: 10/17/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/981,583
• Publication Number:
  US 20030073287A1
• Time in Patent Office: 818 Days
• Field of Search: 438/268, 438/270, 438/272, 257/329, 257/330, 257/331, 257/334, 257/401
• US Class Current: 257/329
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is disclosed. The semiconductor device includes one or more charge control electrodes a plurality of charge control electrodes. The one or more charge control electrodes may control the electric field within the drift region of a semiconductor device.

Claims

1. A semiconductor device comprising:

a) a semiconductor substrate;

b) a first region of a first conductivity type in the semiconductor substrate;

c) a second region of a second conductivity type in the semiconductor substrate, the first and second regions forming a pn junction therebetween;

d) a plurality of charge control electrodes integrated with the semiconductor substrate so as to influence an electric field in one of the first and second regions, wherein at least two of the plurality of charge control electrodes are electrically decoupled from one another so as to be biased differently from one another; and

e) a dielectric material disposed around each of the charge control electrodes.

2. The semiconductor device of claim 1 wherein the semiconductor device is a power diode.

3. The semiconductor device of claim 1 wherein the semiconductor device is a bipolar transistor.

4. The semiconductor device of claim 1 wherein the semiconductor substrate comprises a trench and wherein the charge electrodes in the plurality of charge control electrodes are stacked within the trench.

5. The semiconductor device of claim 1 wherein the first conductivity type is n-type and the second conductivity type is p-type.

6. The semiconductor device of claim 1 wherein each of the plurality of charge control electrodes comprise polysilicon.

7. The semiconductor device of claim 1 wherein the plurality of charge control electrodes are biased to produce a generally uniform electric field in the first region.

22. The semiconductor device of claim 1 further comprising a biasing element coupled to bias the at least two of the plurality of charge control electrodes differently from one another.

23. The semiconductor device of claim 1 wherein at least two of the plurality of charge control electrodes are arranged adjacent to one another parallel to a surface of the semiconductor device.

24. The semiconductor device of claim 23 wherein the plurality of charge control electrodes are in one or more trenches formed in one of the first and second semiconductor regions.

25. The semiconductor device of claim 23 wherein the plurality of charge control electrodes are over but insulated from a surface of one of the first and second semiconductor regions.

26. The semiconductor device of claim 2 wherein the power diode includes an anode electrode coupled to the first region and a cathode electrode coupled to the second region, the plurality of charge control electrodes being located between the anode and cathode electrodes.

8. A field effect transistor comprising:

a) a semiconductor substrate of a first conductivity type having a major surface, a drift region, and a drain region;

b) a well region of a second conductivity type formed in the semiconductor substrate;

c) a source region of the first conductivity type formed in the well region;

d) a gate electrode formed adjacent to the source region;

e) a plurality of stacked charge control electrodes buried within the drift region, wherein at least two of the plurality of stacked charge control electrodes are adapted to be biased differently from one another; and

f) a dielectric material disposed around each of the stacked charge control electrodes.

9. The field effect transistor of claim 8 wherein the plurality of stacked charge control electrodes is directly under the gate electrode.

10. The field effect transistor of claim 8 wherein the gate electrode is a trenched gate electrode.

11. The field effect transistor of claim 8 further comprising a plurality of biasing elements capable of respectively biasing the control electrodes within the plurality of control electrodes.

12. The field effect transistor of claim 8 wherein the plurality of stacked control electrodes is disposed to a side of the gate electrode.

13. The field effect transistor of claim 8 wherein the plurality of stacked control electrodes are a first plurality of stacked control electrodes, and wherein the field effect transistor further includes a second plurality of stacked control electrodes.

14. The field effect transistor of claim 8 wherein the plurality of stacked charge control electrodes is adapted to adjust an electrical field profile within the drift region of the semiconductor substrate so that the magnitude of the electrical field throughout the drift region is generally uniform and exceeds 2×

10⁵ V/cm.

15. The field effect transistor of claim 8 further comprising a trench, wherein the charge control electrodes within the plurality of stacked control electrodes are disposed within the trench.

16. The field effect transistor of claim 8 wherein the field effect transistor is a power metal oxide semiconductor field effect transistor (MOSFET).

17. A field effect transistor comprising:

a) a semiconductor substrate of a first conductivity type having a major surface, a drift region, and a drain region;

b) a well region of a second conductivity type formed in the semiconductor substrate;

c) a source region of the first conductivity type formed in the well region;

d) a source contact layer coupled to the source region;

e) a gate electrode formed adjacent to the source region;

f) a charge control electrode buried in the drift region, wherein the charge control electrode is adapted to be biased at a different potential than the source contact layer, and is adapted to control the electric field in the drift region; and

g) a dielectric material disposed around the charge control electrode.

18. The field effect transistor of claim 17 further comprising a biasing element adapted to bias the charge control electrode at the different potential.

19. The field effect transistor of claim 17 wherein the gate electrode is a trenched gate electrode.

20. The field effect transistor of claim 17 wherein the charge control electrodes is directly under the gate electrode.

21. The field effect transistor of claim 17 wherein the charge control electrode is directly under the gate electrode and wherein the gate electrode is a trenched gate electrode.