Method for implementing a 6-mask cathode process
First Claim
1. In a cathode connection array for a flat panel display, said cathode connection array having a base structure, said base structure comprising an inter-layer dielectric disposed upon a glass substrate, said inter-layer dielectric covering a first metallic conductor, said first metallic conductor disposed upon at least a part of said glass substrate in a first conductor pad area, and a second metallic conductor, said second metallic conductor disposed upon at least a part of said inter-layer dielectric in a second conductor pad area, said second conductor covered by a layer of chromium, a method of forming a direct via for an electrical access to said first and said second metallic conductors, said method comprising:
- depositing a passivation layer upon said base structure;
patterning said passivation layer;
etching said passivation layer accordingly; and
etching said inter-layer dielectric accordingly;
wherein said method does not require deposition of a photoresistive mask for etching said direct via nor process steps corresponding to deposition thereof.
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Accused Products
Abstract
One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a direct via masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required direct via masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time. Advantageously, this increases efficiency and productivity, correspondingly reducing fabrication costs and unit costs of finished devices.
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Citations
20 Claims
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1. In a cathode connection array for a flat panel display, said cathode connection array having a base structure, said base structure comprising an inter-layer dielectric disposed upon a glass substrate, said inter-layer dielectric covering a first metallic conductor, said first metallic conductor disposed upon at least a part of said glass substrate in a first conductor pad area, and a second metallic conductor, said second metallic conductor disposed upon at least a part of said inter-layer dielectric in a second conductor pad area, said second conductor covered by a layer of chromium, a method of forming a direct via for an electrical access to said first and said second metallic conductors, said method comprising:
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depositing a passivation layer upon said base structure;
patterning said passivation layer;
etching said passivation layer accordingly; and
etching said inter-layer dielectric accordingly;
wherein said method does not require deposition of a photoresistive mask for etching said direct via nor process steps corresponding to deposition thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. In a cathode connection array for a cathode of a flat panel display, said cathode connection array having a base structure, said base structure comprising an inter-layer dielectric disposed upon a glass substrate, said inter-layer dielectric covering a first metallic conductor, said first metallic conductor disposed upon at least a part of said glass substrate in a first conductor pad area, and a second metallic conductor disposed upon at least a part of said inter-layer dielectric in a second conductor pad area, said second conductor covered by a layer of chromium, an electrical access product formed by a process for forming a direct via, said process implementing a method comprising:
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depositing a passivation layer upon said base structure;
patterning said passivation layer;
etching said passivation layer accordingly; and
etching said inter-layer dielectric accordingly;
wherein said method does not require deposition of a photoresistive mask for etching said direct via nor process steps corresponding to deposition thereof. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification