Method for implementing a 6-mask cathode process

• US 6,677,705 B2
• Filed: 09/28/2001
• Issued: 01/13/2004
• Est. Priority Date: 09/28/2001
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.), Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Candescent Intellectual Property Services, Inc., Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Bonn, Matthew A., Lee, Jueng-Gil, Kikuchi, Kazuo
• Primary Examiner(s): Ramsey, Kenneth J.
• Application Number:
  US09/968,221
• Publication Number:
  US 20030064655A1
• Time in Patent Office: 837 Days
• Field of Search: 445/24, 313/309, 313/495, 313/422
• US Class Current: 313/495
• CPC Class Codes: H01J 9/025 of field emission cathodes

Abstract

One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a direct via masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required direct via masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time. Advantageously, this increases efficiency and productivity, correspondingly reducing fabrication costs and unit costs of finished devices.

Claims

1. In a cathode connection array for a flat panel display, said cathode connection array having a base structure, said base structure comprising an inter-layer dielectric disposed upon a glass substrate, said inter-layer dielectric covering a first metallic conductor, said first metallic conductor disposed upon at least a part of said glass substrate in a first conductor pad area, and a second metallic conductor, said second metallic conductor disposed upon at least a part of said inter-layer dielectric in a second conductor pad area, said second conductor covered by a layer of chromium, a method of forming a direct via for an electrical access to said first and said second metallic conductors, said method comprising:

depositing a passivation layer upon said base structure;

patterning said passivation layer;

etching said passivation layer accordingly; and

etching said inter-layer dielectric accordingly;

wherein said method does not require deposition of a photoresistive mask for etching said direct via nor process steps corresponding to deposition thereof.

2. The method as recited in claim 1, wherein said passivation layer comprises nitrides of silicon.

3. The method as recited in claim 2, wherein said etching said passivation layer accordingly comprises performing a nitrides of silicon dry etch.

4. The method as recited in claim 3, wherein said performing a nitrides of silicon dry etch comprises application of a gas mixture.

5. The method as recited in claim 4, wherein said gas mixture comprises sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, and oxygen.

6. The method as recited in claim 4, wherein said gas mixture comprises octafluorocyclobutane, carbon monoxide, argon.

7. The method as recited in claim 6, wherein said gas mixture further comprises nitrogen.

8. The method as recited in claim 1, wherein said base structure further comprises a resistor disposed between said glass substrate and said inter-layer dielectric, and between said first metallic conductor and said inter-layer dielectric.

9. The method as recited in claim 8, wherein said method further comprises performing a dual resistor etch.

10. The method as recited in claim 1, wherein said etching said inter-layer dielectric accordingly further comprises performing an inter-layer dielectric wet etch.

11. In a cathode connection array for a cathode of a flat panel display, said cathode connection array having a base structure, said base structure comprising an inter-layer dielectric disposed upon a glass substrate, said inter-layer dielectric covering a first metallic conductor, said first metallic conductor disposed upon at least a part of said glass substrate in a first conductor pad area, and a second metallic conductor disposed upon at least a part of said inter-layer dielectric in a second conductor pad area, said second conductor covered by a layer of chromium, an electrical access product formed by a process for forming a direct via, said process implementing a method comprising:

depositing a passivation layer upon said base structure;

patterning said passivation layer;

etching said passivation layer accordingly; and

etching said inter-layer dielectric accordingly;

wherein said method does not require deposition of a photoresistive mask for etching said direct via nor process steps corresponding to deposition thereof.

12. The product as recited in claim 11, wherein said passivation layer comprises nitrides of silicon.

13. The product as recited in claim 12, wherein said etching said passivation layer accordingly of said method comprises performing a nitrides of silicon dry etch.

14. The product as recited in claim 13, wherein said performing a nitrides of silicon dry etch of said method comprises application of a gas mixture.

15. The product as recited in claim 14, wherein said gas mixture comprises sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, and oxygen.

16. The product as recited in claim 14, wherein said gas mixture comprises octafluorocyclobutane, carbon monoxide, argon.

17. The product as recited in claim 16, wherein said gas mixture further comprises nitrogen.

18. The product as recited in claim 11, wherein said base structure further comprises a resistor disposed between said glass substrate and said inter-layer dielectric, and between said first metallic conductor and said inter-layer dielectric.

19. The product as recited in claim 18, wherein said method further comprises performing a dual resistor etch.

20. The product as recited in claim 11, wherein said etching said inter-layer dielectric accordingly of said method further comprises performing an inter-layer dielectric wet etch.