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Circuit for selectively enabling and disabling coils of a multi-coil array

  • US 6,677,755 B2
  • Filed: 09/30/2002
  • Issued: 01/13/2004
  • Est. Priority Date: 11/26/1997
  • Status: Expired due to Fees
First Claim
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1. A circuit for selectively enabling and disabling n-coils, said circuit comprising:

  • (a) n-drivers powered by a current source, each of said n-drivers having an N-channel FET and a P-channel FET disposed such that a gate of said N-channel FET is connected to a gate of said P-channel FET to form a common gate node thereat, said n-drivers disposed in a totem-pole configuration such that;

    (i) said N-channel FET of a first of said n-drivers has (A) a drain thereof linked to a ground and to an end of a first of said n-coils and (B) a source thereof linked to a drain of said N-channel FET of a second of said n-drivers and to an end of a second of said n-coils;

    (ii) said P-channel FET of said first of said n-drivers has (A) a source thereof linked to an opposite end of said first of said n-coils and (B) a drain thereof linked to said end of said second of said n-coils and to said source of said N-channel FET of said first of said n-drivers;

    (iii) said N-channel FET of said second of said n-drivers also having (A) a source thereof linked to a drain of said N-channel FET of a next of said n-drivers and to an end of a next of said n-coils, said P-channel FET of said second of said n-drivers also having (A) a source thereof linked to an opposite end of said second of said n-coils and (B) a drain thereof linked to said end of said next of said n-coils and to said source of said N-channel FET of said second of said n-drivers; and

    (iv) continuing until said N-channel FET and said P-channel FET of an nth of said n-drivers are likewise disposed in said totem-pole configuration of said n-drivers with a source and a drain of said N-channel FET and said P-channel FET, respectively, of said nth of said n-drivers being connected to said current source; and

    (b) each of said n-drivers for operating a corresponding one of said n-coils by being responsive at said common gate node therefor to (i) a coil disable signal by activating said N-channel FET thereof and deactivating said P-channel FET thereof thereby not only drawing current away from and thus disabling said corresponding coil but also allowing said current to flow through said N-channel FET and thus be available as a source of current to a successive one of said n-drivers and (ii) a coil enable signal by deactivating said N-channel FET thereof and activating said P-channel FET thereof thereby allowing said current not only to flow serially through said corresponding coil and said P-channel FET thus enabling said corresponding coil but also to be available as a source of current to said successive one of said n-drivers.

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