Circuit for selectively enabling and disabling coils of a multi-coil array

• US 6,677,755 B2
• Filed: 09/30/2002
• Issued: 01/13/2004
• Est. Priority Date: 11/26/1997
• Status: Expired due to Fees

• Current Assignee: Medrad Incorporated (Bayer AG)
• Original Assignee: Medrad Incorporated (Bayer AG)
• Inventors: Adams, Bradley J., Watral, J. Michael, Augustine, Lisa A., Reichel, Michael, Bell, Robert S. Jr., Belt, Kenneth W., Lewandowski, Stanley R.
• Primary Examiner(s): Arana, Louis
• Application Number:
  US10/260,787
• Publication Number:
  US 20030117140A1
• Time in Patent Office: 470 Days
• Field of Search: 324/322, 324/318, 324/314, 324/300, 324/306, 324/307, 324/309, 324/312, 600/420, 600/421, 600/422, 600/410
• US Class Current: 324/322
• CPC Class Codes: G01R 33/3415 comprising arrays of sub-coils , i.e. phased-array coils with flexible receiver channels

Abstract

A circuit for selectively disabling and enabling n-coils includes n-drivers disposed in a totem-pole configuration. Each of the n-drivers includes two FETs whose gates connect at a common node therefor. Each n-driver is used to operate one of the n-coils by being responsive at its common node to (i) a coil disable signal by activating one FET thereof and deactivating the other FET thereof drawing current away from and thus disabling its corresponding coil and allowing current to flow through the one FET and thus be available as a source of current to a successive one of the n-drivers and (ii) a coil enable signal by deactivating the one FET thereof and activating the other FET thereof thereby allowing current to flow serially through its corresponding coil and the other FET thus enabling its corresponding coil and to be available as a source of current to the successive n-driver.

Claims

1. A circuit for selectively enabling and disabling n-coils, said circuit comprising:

(a) n-drivers powered by a current source, each of said n-drivers having an N-channel FET and a P-channel FET disposed such that a gate of said N-channel FET is connected to a gate of said P-channel FET to form a common gate node thereat, said n-drivers disposed in a totem-pole configuration such that;

(i) said N-channel FET of a first of said n-drivers has (A) a drain thereof linked to a ground and to an end of a first of said n-coils and (B) a source thereof linked to a drain of said N-channel FET of a second of said n-drivers and to an end of a second of said n-coils;

(ii) said P-channel FET of said first of said n-drivers has (A) a source thereof linked to an opposite end of said first of said n-coils and (B) a drain thereof linked to said end of said second of said n-coils and to said source of said N-channel FET of said first of said n-drivers;

(iii) said N-channel FET of said second of said n-drivers also having (A) a source thereof linked to a drain of said N-channel FET of a next of said n-drivers and to an end of a next of said n-coils, said P-channel FET of said second of said n-drivers also having (A) a source thereof linked to an opposite end of said second of said n-coils and (B) a drain thereof linked to said end of said next of said n-coils and to said source of said N-channel FET of said second of said n-drivers; and

(iv) continuing until said N-channel FET and said P-channel FET of an nth of said n-drivers are likewise disposed in said totem-pole configuration of said n-drivers with a source and a drain of said N-channel FET and said P-channel FET, respectively, of said nth of said n-drivers being connected to said current source; and

(b) each of said n-drivers for operating a corresponding one of said n-coils by being responsive at said common gate node therefor to (i) a coil disable signal by activating said N-channel FET thereof and deactivating said P-channel FET thereof thereby not only drawing current away from and thus disabling said corresponding coil but also allowing said current to flow through said N-channel FET and thus be available as a source of current to a successive one of said n-drivers and (ii) a coil enable signal by deactivating said N-channel FET thereof and activating said P-channel FET thereof thereby allowing said current not only to flow serially through said corresponding coil and said P-channel FET thus enabling said corresponding coil but also to be available as a source of current to said successive one of said n-drivers.

2. The circuit of claim 1 further comprising:

(a) a PIN diode within each of said n-coils, each of said PIN diodes capable of being biased to actively decouple said coil corresponding thereto from a radio frequency field generated during a transmit cycle of a magnetic resonance imaging (MRI) system; and

(b) a diode connected serially with said N-channel FET corresponding thereto;

so that for each of said n-drivers a voltage drop and a current flow therethrough is substantially equal whether said current is flowing through (i) said P-channel FET and said corresponding coil or (ii) said N-channel FET.

3. The circuit of claim 2 wherein each of said n-drivers further comprises an upper error state switch and a lower error state switch for sensing at least one of (i) when said PIN diode corresponding thereto is opened, (ii) when said PIN diode corresponding thereto is shorted, (iii) when either of said N-channel FET or said P-channel FET corresponding thereto is opened, and (iv) when either of said N-channel FET or said P-channel FET corresponding thereto is shorted.

4. The circuit of claim 3 wherein in each of said n-drivers said upper error state switch is connected to said drain of said N-channel FET thereof and said lower error state switch is connected to said source of said P-channel FET thereof.

5. The circuit of claim 1 further comprising a comparator for monitoring said current through said n-drivers and detecting (i) a short condition when said current flowing therethrough is higher than an upper predetermined level and (ii) an open condition when said current flowing therethrough is lower than a lower predetermined level.

6. A circuit for selectively enabling and disabling n-coils, said circuit comprising:

(a) n-drivers powered by a current source, each of said n-drivers having a pair of FETs disposed such that a gate of one of said FETs is connected to a gate of an other of said FETs to form a common gate node thereat, said n-drivers disposed in a totem-pole configuration such that;

(i) said one FET of a first of said n-drivers has (A) a drain thereof linked to a ground and to an end of a first of said n-coils and (B) a source thereof linked to a drain of said one FET of a second of said n-drivers and to an end of a second of said n-coils;

(ii) said other FET of said first of said n-drivers has (A) a source thereof linked to an opposite end of said first of said n-coils and (B) a drain thereof linked to said end of said second of said n-coils and to said source of said one FET of said first of said n-drivers;

(iii) said one FET of said second of said n-drivers also having (A) a source thereof linked to a drain of said one FET of a next of said n-drivers and to an end of a next of said n-coils, said other FET of said second of said n-drivers also having (A) a source thereof linked to an opposite end of said second of said n-coils and (B) a drain thereof linked to said end of said next of said n-coils and to said source of said one FET of said second of said n-drivers; and

(iv) continuing until said one FET and said other FET of an nth of said n-drivers are likewise disposed in said totem-pole configuration of said n-drivers with a source and a drain of said one FET and said other FET, respectively, of said nth of said n-drivers being connected to said current source; and

(b) each of said n-drivers for operating a corresponding one of said n-coils by being responsive at said common gate node therefor to (i) a coil disable signal by activating said one FET thereof and deactivating said other FET thereof thereby not only drawing current away from and thus disabling said corresponding coil but also allowing said current to flow through said one FET and thus be available as a source of current to a successive one of said n-drivers and (ii) a coil enable signal by deactivating said one FET thereof and activating said other FET thereof thereby allowing said current not only to flow serially through said corresponding coil and said other FET thus enabling said corresponding coil but also to be available as a source of current to said successive one of said n-drivers.

7. The circuit of claim 6 further comprising:

(a) a PIN diode within each of said n-coils, each of said PIN diodes capable of being biased actively decouple said coil corresponding thereto from a radio frequency field generated during a transmit cycle of a magnetic resonance imaging (MRI) system; and

(b) a diode connected serially with said one FET corresponding thereto;

so that for each of said n-drivers a voltage drop and a current flow therethrough is substantially equal whether said current is flowing through (i) said other FET and said corresponding coil or (ii) said one FET.

8. The circuit of claim 7 wherein each of said n-drivers further comprises an upper error state switch and a lower error state switch for sensing at least one of (i) when said PIN diode corresponding thereto is opened, (ii) when said PIN diode corresponding thereto is shorted, (iii) when either of said one FET or said other FET corresponding thereto is opened, and (iv) when either of said one FET or said other FET corresponding thereto is shorted.

9. The circuit of claim 8 wherein in each of said n-drivers said upper error state switch is connected to said drain of said one FET thereof and said lower error state switch is connected to said source of said other FET thereof.

10. The circuit of claim 6 further comprising a comparator for monitoring said current through said n-drivers and detecting (i) a short condition when said current flowing therethrough is higher than an upper predetermined level and (ii) an open condition when said current flowing therethrough is lower than a lower predetermined level.

12. The circuit of claim 10 further comprising:

(a) a PIN diode within each of said n-coils, each of said PIN diodes capable of being biased to actively decouple said coil corresponding thereto from a radio frequency field generated during a transmit cycle of a magnetic resonance imaging (MRI) system; and

(b) a diode connected serially with said one FET corresponding thereto;

so that for each of said n-drivers a voltage drop and a current flow therethrough is substantially equal whether said current is flowing through (i) said other FET and said corresponding coil or (ii) said one FET.

13. The circuit of claim 12 wherein each of said n-drivers further comprises an upper error state switch and a lower error state switch for sensing at least one of (i) when said PIN diode corresponding thereto is opened, (ii) when said PIN diode corresponding thereto is shorted, (iii) when either of said one FET or said other PET corresponding thereto is opened, and (iv) when either of said one FET or said other PET corresponding thereto is shorted.

14. The circuit of claim 13 wherein in each of said n-drivers said upper error state switch is connected to said drain of said one FET thereof and said lower error state switch is connected to said source of said other FET thereof.

11. A circuit for selectively enabling and disabling n-coils of an array of imaging coils for use with a magnetic resonance imaging (MRI) system, said circuit comprising:

(a) a relatively positive power source;

(b) a relatively negative power source;

(c) n-drivers for driving said n-coils of said array, each of said n-drivers having a pair of FETs disposed such that a gate of one of said FETs is connected to a gate of an other of said FETs to form a common gate node thereat, said n-drivers disposed in a totem-pole configuration such that;

(i) said one FET of a first of said n-drivers has (A) a drain linked to said relatively positive power source and to an end of a first of said n-coils and (B) a source linked to a drain of said one FET of a second of said n-drivers and to an end of a second of said n-coils;

(ii) said other FET of said first of said n-drivers has (A) a source linked to an opposite end of said first of said n-coils and (B) a drain linked to said end of said second of said n-coils and to said source of said one FET of said first of said n-drivers;

(iii) said one FET of said second of said n-drivers also having (A) a source linked to a drain of said one FET of a next of said n-drivers and to an end of a next of said n-coils, said other FET of said second of said n-drivers also having (A) a source linked to an opposite end of said second of said n-coils and (B) a drain linked to said end of said next of said n-coils and to said source of said one FET of said second of said n-drivers; and

(iv) continuing until said one FET and said other FET of an nth of said n-drivers are likewise disposed in said totem-pole configuration of said n-drivers with a source and a drain of said one FET and said other FET, respectively, of said nth of said n-drivers being connected to said relatively negative power source; and

(d) each of said n-drivers for operating a corresponding one of said n-coils by being responsive at said common gate node therefor to (i) a coil disable signal by activating said one FET thereof and deactivating said other FET thereof thereby not only drawing current away from and thus disabling said corresponding coil but also allowing said current to flow through said one FET and thus be available as a source of current to a successive one of said n-drivers and (ii) a coil enable signal by deactivating said one FET thereof and activating said other FET thereof thereby allowing said current not only to flow through said corresponding coil and said other FET thus enabling said corresponding coil but also to be available as a source of current to said successive one of said n-drivers.

15. The circuit of claim 11 further comprising a comparator for monitoring said current through said n-drivers and detecting (i) a short condition when said current flowing therethrough is higher than an upper predetermined level and (ii) an open condition when said current flowing therethrough is lower than a lower predetermined level.

16. A circuit for selectively enabling and disabling n-coils, said circuit comprising:

(a) n-drivers disposed in a totem-pole configuration and powered by a current source, each of said n-drivers having a current source connection and a current sink connection such that (i) a first of said n-drivers is linked via said current source connection therefor to said current source, (ii) a next of said n-drivers is linked via said current source connection therefor and said current sink connection of said first of said n-drivers to said current source, and (iii) continuing until an nth of said n-drivers is linked via said current source connection therefor and said current sink connection of an (n−

1)th of said n-drivers to said current source; and

(b) each of said n-drivers for operating a corresponding one of said n-coils by being responsive to (i) a coil enable signal by providing current to said coil corresponding thereto via said current source connection therefor thereby enabling said coil corresponding thereto and (ii) a coil disable signal by drawing current away from said coil corresponding thereto via said current sink connection therefor thereby disabling said coil corresponding thereto.