Method and apparatus for implementing precision time delays
First Claim
1. A system of implementing precision time delays, comprising:
- a clock input, said clock input being split into at least two separate clock inputs with a specified phase shift therebetween;
a delay count providing input to a first lookup table, said first lookup table providing a first output to a first digital to analog converter, the output of said first digital to analog converter being multiplied with at least one of said at least two separate clock inputs thereby providing a first multiplied signal, said first lookup table also providing a second output to a second digital to analog converter, the output of said second digital to analog converter being multiplied with a second of said at least two separate clock inputs to provide a second multiplied signal;
an addition and output means to add said first multiplied signal to said second multiplied signal;
a variable threshold, said variable threshold receiving as one input the output of said addition and output means; and
a second lookup table, said second lookup table'"'"'s output providing a second input to said variable threshold, thereby enabling a desired delayed output signal from said variable threshold.
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Abstract
A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals. The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. There is provided herein an optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits.
128 Citations
27 Claims
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1. A system of implementing precision time delays, comprising:
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a clock input, said clock input being split into at least two separate clock inputs with a specified phase shift therebetween;
a delay count providing input to a first lookup table, said first lookup table providing a first output to a first digital to analog converter, the output of said first digital to analog converter being multiplied with at least one of said at least two separate clock inputs thereby providing a first multiplied signal, said first lookup table also providing a second output to a second digital to analog converter, the output of said second digital to analog converter being multiplied with a second of said at least two separate clock inputs to provide a second multiplied signal;
an addition and output means to add said first multiplied signal to said second multiplied signal;
a variable threshold, said variable threshold receiving as one input the output of said addition and output means; and
a second lookup table, said second lookup table'"'"'s output providing a second input to said variable threshold, thereby enabling a desired delayed output signal from said variable threshold. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of implementing precision time delays, comprising the steps of:
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splitting a clock input into at least two separate clock inputs with a specified phase shift therebetween;
inputting a delay count into a first lookup table, said lookup table providing a first off circle scaling factor to a first digital to analog converter, the output of said first digital to analog converter being multiplied with at least one of said at least two separate clock inputs thereby providing a first multiplied signal, said lookup table also providing a second off circle scaling factor to a second digital to analog converter, the output of said second digital to analog converter being multiplied with a second of said at least two separate clock inputs to provide a second multiplied signal;
adding said first multiplied signal to said second multiplied signal and outputing said added signal;
using a variable threshold to receive as one input the output of said addition and output means; and
providing a second lookup table, said second lookup table'"'"'s output providing a second input to said variable threshold, thereby enabling a desired delayed output signal from said variable threshold. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification