Systems and methods for communicating with memory blocks

• US 6,678,200 B2
• Filed: 05/14/2002
• Issued: 01/13/2004
• Est. Priority Date: 05/14/2002
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Perner, Frederick A.
• Primary Examiner(s): Lam, David
• Application Number:
  US10/145,834
• Publication Number:
  US 20030214869A1
• Time in Patent Office: 609 Days
• Field of Search: 365/209, 365/230.03, 365/230.06, 365/189.01, 365/189.07, 365/158, 365/157
• US Class Current: 365/209
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Systems and methods for reading from or writing to memory blocks, are provided. An embodiment of the system comprises a plurality of memory blocks; a plurality of repeaters; and a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks. One embodiment of the method comprises coupling the memory blocks to repeaters; and reading from the memory blocks.

Claims

1. A memory device, comprising:

a plurality of memory blocks;

a plurality of repeaters; and

a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks;

wherein at least one of the repeaters comprises a comparator, access transistors, and at least one drive transistor, and wherein one repeater is configured to sense voltage at an output of each memory block, and to provide a voltage to each node of the line.

2. The device of claim 1, wherein the memory blocks are magnetic random access memory (MRAM) blocks.

3. The device of claim 1, wherein the repeators are configured to sense whether the line is selected, and if the line is selected, provide a voltage to the line.

4. The device of claim 1, wherein the line is configured by coupling word lines of the memory blocks to each other, a word line of one of the memory blocks having a same address as addresses of word lines of remaining memory blocks.

5. The device of claim 1, wherein the line couples a decoder, the repeaters, and the memory blocks, wherein the memory blocks are in series with the repeaters and the decoder, and wherein one repeater is located adjacent to each memory block.

6. A system for communicating with memory blocks of a memory device, the system comprising:

means for reading from the memory blocks; and

means for coupling the memory blocks to the means for reading;

wherein the means for reading comprises a comparator and access transistors to sense voltage at an output of each memory block, and further comprises at least one drive transistor to provide a voltage to the means for coupling.

7. The system of claim 6, wherein the memory blocks are magnetic random access memory (MRAM) blocks.

8. The system of claim 6, wherein the means for reading are configured to sense whether the means for coupling is selected, and if the means for coupling is selected, a voltage is provided to the means for coupling.

9. The system of claim 6, wherein the means for coupling is configured by coupling word lines of the memory blocks to each other, a word line of one of the memory blocks having a same address as addresses of word lines of remaining memory blocks.

10. The system of claim 6, wherein the means for coupling couples a decoder, the means for reading, and the memory blocks, wherein the memory blocks are in series with the means for reading and the decoder, and wherein a means for reading is located adjacent to each memory block.