MPEG decoder using a shared memory

• US 6,678,331 B1
• Filed: 11/02/2000
• Issued: 01/13/2004
• Est. Priority Date: 11/03/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Moutin, Jean-Michel, Marty, Pierre
• Primary Examiner(s): Le, Vu
• Application Number:
  US09/705,338
• Time in Patent Office: 1,167 Days
• Field of Search: 375/240.25, 375/240.26, 375/240.28, 375/240.29, 709/102-103, 709/212-215, 709/247, 710/40, 710/240-244, 710/113-114, 711/147-153, 711/158
• US Class Current: 375/240.25
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A circuit includes a microprocessor, an MPEG decoder for decoding an image sequence, and a memory common to the microprocessor and to the decoder. The circuit also includes a circuit for evaluating a decoder delay, a control circuit for, if the decoder delay is greater than a predetermined level, granting the decoder a memory access priority, and otherwise, granting the microprocessor the memory access priority.

Claims

1. A circuit including a microprocessor, an MPEG decoder for decoding an image sequence, and a memory common to the microprocessor and to the decoder, comprising:

an evaluation circuit for evaluating a decoder delay of the MPEG decoder; and

,

a control circuit for, if the decoder delay is greater than a predetermined level, granting the decoder a memory access priority, and otherwise, granting the microprocessor the memory access priority.

2. The circuit of claim 1, including a clock, means for determining a reference period equal to a determined number of clock cycles, means for determining an activity threshold, wherein the circuit for evaluating the decoder delay includes:

means for determining during each clock cycle whether the decoder is used or unused,

a counter having a count value incremented each time the decoder is unused during a clock cycle,

a subtractor which, at the beginning of each reference period, subtracts said activity threshold from the count valve, and

a comparator for checking whether the count valve remains negative, the output of this comparator being provided to the control circuit.

3. The circuit of claim 1, further including additional circuits that use the memory via the control circuit at predetermined access time periods, wherein the control circuit is provided to alternately grant access to the memory to the additional circuits, then to the microprocessor and to the decoder, the access to the memory by the microprocessor and the decoder being controlled by a control signal generated by the evaluation circuit.

4. A method of sharing a common memory between a microprocessor and an image decoder for decoding an image sequence, the method comprising:

communicatively linking the memory to a control circuit, the control circuit controlling access to the memory;

communicatively linking the image decoder to the control circuit;

communicatively linking the microprocessor to the control circuit;

evaluating an image decoder delay of the image decoder; and

providing a control signal to the control circuit, the control signal configured to instruct the control circuit to grant the image decoder a memory access priority only when the image decoder delay is greater than a predetermined level, and otherwise grant the microprocessor the memory access priority.

5. The method of claim 4 wherein evaluating the image decoder delay includes:

generating a clock signal;

determining a reference period equal to a determined number of clock cycles;

determining an activity threshold value;

determining whether the image decoder is unused during a clock cycle;

updating a count value each time the image decoder is unused during a clock cycle;

adjusting the count value with the activity threshold value;

checking the sign of the count value; and

generating the control signal based on the sign on the count value.

6. The method of claim 5 wherein updating is performed once each reference period.

7. The method of claim 5 wherein a state machine determines when updating occurs.

8. The method of claim 5 wherein updating means incrementing.

9. The method of claim 5 wherein adjusting the count value with the activity threshold value means subtracting the activity threshold value from the count value.

10. The method of claim 5 wherein the control signal is configured to grant the microprocessor memory access priority when the sign of the count value is negative.

11. The method of claim 4, further comprising:

sharing the memory with a plurality of additional circuits;

dividing the memory access priority into access time periods;

assigning each additional circuit a predetermined number of access time periods; and

assigning the microprocessor and the image decoder a predetermined number of access time periods to share together.

12. The method of claim 4 wherein the image decoder is a MPEG decoder.

13. A circuit for evaluating a delay of an image decoder comprising:

an activity determination circuit that determines whether the image decoder is unused during a clock cycle;

a counter that is coupled to the activity determination circuit and structured to update a count value when the image decoder is unused during a clock cycle;

an arithmetic logic unit that adjusts the count value with an activity threshold value once a reference period; and

a comparator for determining a sign of the count value.

14. The circuit of claim 13 further including:

a means for determining the activity threshold value;

a means for determining the reference period equal to a determined number of clock cycles.

15. The circuit of claim 13 further including:

a state machine, the state machine used to instruct the arithmetic logic unit when to adjust the count value with the activity threshold value.

16. The circuit of claim 13 wherein the comparator generates a control signal that instructs a control circuit to grant a memory access priority to the image decoder only when the image decoder delay is greater than a predetermined level, and otherwise granting the microprocessor the memory access priority.

17. The circuit of claim 13 wherein the updating the count value means incrementing the count value.

18. The circuit of claim 13 wherein the arithmetic logic unit is a subtractor that subtracts the activity threshold value from the count value.

19. The circuit of claim 13, further comprising a controller that grants wherein the microprocessor a memory access priority when the sign of the count value is negative.

20. The circuit of claim 13 wherein the image decoder is an MPEG decoder.

21. A method of sharing a common memory between a microprocessor and an image decoder for decoding an image sequence, the method comprising:

determining an image decoder delay based on an activity level of the image decoder;

granting the image decoder a memory access priority only when the image decoder delay is greater than a predetermined level, thereby temporarily debasing microprocessor performance; and

otherwise granting the microprocessor the memory access priority.

22. The method of claim 21 wherein a plurality of additional circuits can further share the common memory by dividing the memory access priority into access time periods, each additional circuit being assigned a predetermined number of access time periods and the microprocessor and the image decoder being assigned a predetermined number of access time periods to share together.

23. The method of claim 21 wherein the image decoder is a MPEG decoder.