Power on self test (POST) and extended self test (EST) for ultrasonic imaging system

• US 6,678,626 B2
• Filed: 07/31/2001
• Issued: 01/13/2004
• Est. Priority Date: 07/31/2001
• Status: Expired due to Fees

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Martin, William R., McKernan, Thomas P., Fallon, Joseph R, Powell, Melissa A.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): West, Jeffrey R
• Application Number:
  US09/919,466
• Publication Number:
  US 20030028341A1
• Time in Patent Office: 896 Days
• Field of Search: 702/108, 702/113, 702/115, 702/116, 702/117, 702/119, 702/57, 702/58, 702/118, 702/120, 702/123, 702/124, 702/182, 702/185, 736/06, 736/07, 736/18, 736/20, 735/96, 367/137, 367/138, 600/437-472
• US Class Current: 702/117
• CPC Class Codes: G01S 7/52034 Data rate converters
• CPC Class Codes: G01S 7/5205 Means for monitoring or calibrating

Abstract

An ultrasonic imaging system including a power on self test (POST) and an extended self test (EST). The POST includes (a) a verification test, (b) a register test (c) a controller test, (d) a receive digital signal path test and (e) a basic front end test. The POST is initiated, performed and completed within a short time, such as three seconds, from power ON. The EST is performed after the POST at the discretion of an operator, and includes a transmit test, a transducer element test, a front end voltage test and a receive test.

Claims

1. An ultrasonic imaging system comprising:

a first on-board memory storing run-time code;

a second on-board memory having a faster access time than the first on-board memory;

a first application specific integrated circuit (ASIC) including a beamformer, first and second built-in pseudo-random number (PRN) generators, and a first built-in cyclic redundancy coding checker, and

a second application specific integrated circuit (ASIC) including a detector and a second built-in cyclic redundancy coding (CRC) checker; and

a power on self test (POST) which is initiated, performed and completed within three seconds of power ON, wherein the run-time code is configured to perform the POST and ultrasonic scanning with said ultrasonic imaging system, further wherein the POST includes a verification test for copying the run-time code from the first on-board memory to the second on-board memory enabling access to the run-time code from said faster second on-board memory, the verification test further for verifying that the copied run-time code has been copied correctly, and wherein a receive digital signal path during ultrasonic scanning passes through the beamformer and then the detector, wherein the POST further including a receive digital signal path test in which the first PRN generator and first CRC checker operate with the second PRN generator and second CRC checker to test an output of the beamformer and an output of the detector of the receive digital signal path, respectively, in parallel.

2. The ultrasonic imaging system as in claim 1, wherein, after completion of the POST, further diagnostic tests are not required for the ultrasonic imaging system to perform ultrasonic scanning.

3. The ultrasonic imaging system as in claim 1, further comprising:

a back-end application specific integrated circuit (ASIC) including registers to perform ultrasonic scanning, the POST including a register test to test the registers, the register test being initiated, performed and completed after completion of the verification test.

4. The ultrasonic imaging system as in claim 3, wherein the ultrasonic imaging system further comprises a controller generating a real-time clock and controlling input/output operations during ultrasonic scanning, the POST including a controller test testing operation of the controller, the controller test being initiated, performed and completed after completion of the register test.

5. The ultrasonic imaging system as in claim 4, wherein the receive digital signal path test is initiated, performed and completed after completion of the controller test.

6. The ultrasonic imaging system as in claim 5, wherein the POST includes a basic front end test which is initiated, performed and completed after completion of the receive digital signal path test.

7. The ultrasonic imaging system as in claim 1, further comprising an extended self-test (EST) performed at the discretion of an operator after completion of the POST, the EST including at least one of the group consisting of a transmit test, a transducer element test, a front end voltage test and a receive test.

8. The ultrasonic imaging system as in claim 1, further comprising an extended self-test (EST) performed at the discretion of an operator after completion of the POST, the EST including a transmit test, a transducer element test, a front end voltage test and a receive test.

9. The ultrasonic imaging system as in claim 1, further comprising an extended self-test (EST) performed at the discretion of an operator after completion of the POST, the EST including

a transmit test,

a transducer element test which is initiated, performed and completed after completion of the transmit test,

a front end voltage test which is initiated, performed and completed after completion of the transducer element test, and

a receive test which is initiated, performed and completed after completion of the front end voltage test.

10. An ultrasonic imaging system comprising:

a first on-board memory storing run-time code;

a second on-board memory having a faster access time than the first on-board memory, the run-time code being moved from the first on-board memory to the second on-board memory to perform ultrasonic scanning;

a first application specific integrated circuit (ASIC) including a beamformer, first and second built-in pseudo-random number (PRN) generators, and a first built-in cyclic redundancy coding checker, and

a second application specific integrated circuit (ASIC) including a detector and a second built-in cyclic redundancy coding (CRC) checker; and

a power on self test (POST) including a verification test which copies the run-time code from the first on-board memory to the second on-board memory and verifies that the copied run-time code has been copied correctly, wherein the run-time code is configured to perform the POST and ultrasonic scanning, and wherein copying the run-time code from the first on-board memory to the second on-board memory enables access to the run-time code from the faster second on-line memory, and wherein a receive digital signal path during ultrasonic scanning passes through the beamformer and then the detector, wherein the POST further including a receive digital signal path test in which the first PRN generator and first CRC checker operate with the second PRN generator and second CRC checker to test an output of the beamformer and an output of the detector of the receive digital signal path, respectively, in parallel.

11. The ultrasonic imaging system as in claim 10, further comprising:

a back-end application specific integrated circuit (ASIC) including registers to perform ultrasonic scanning, the POST including a register test to test the registers, the register test being initiated, performed and completed after completion of the verification test.

12. The ultrasonic imaging system as in claim 11, wherein the ultrasonic imaging system further comprises a controller generating a real-time clock and controlling input/output operations during ultrasonic scanning, the POST including a controller test testing operation of the controller, the controller test being initiated, performed and completed after completion of the register test.

13. The ultrasonic imaging system as in claim 12, wherein the receive digital signal path test being initiated, performed and completed after completion of the controller test.

14. The ultrasonic imaging system as in claim 13, wherein the POST includes a basic front end test which is initiated, performed and completed after completion of the receive digital signal path test.

15. An ultrasonic imaging system comprising:

a first application specific integrated circuit (ASIC) including a beamformer, first and second built-in pseudo-random number (PRN) generators, and a first built-in cyclic redundancy coding checker, and

a second application specific integrated circuit (ASIC) including a detector and a second built-in cyclic redundancy coding (CRC) checker; and

a power on self test (POST) including

a verification test for copying run-time code from a first on-board memory to a second on-board memory and verifying that the copied run-time code has been copied correctly, the second on-board memory having a faster access time than the first on-board memory, and wherein the run-time code is configured to perform the POST and ultrasonic scanning,

a register test testing registers included in an application specific integrated circuit (ASIC) for performing ultrasonic scanning according to the run-time code,

a controller test testing operation of a controller which generates a real-time clock and controls input/output operations during ultrasonic scanning according to the run-time code,

a receive digital signal path test testing a receive digital signal path between a beamformer and a detector of the ultrasonic imaging system according to the run-time code, and

a basic front end test for testing a receive path through an analog front end of the ultrasonic imaging system according to the run-time code, wherein the receive digital signal path test includes the first PRN generator and first CRC checker configured to operate with the second PRN generator and second CRC checker to test an output of the beamformer and an output of the detector of the receive digital signal path, respectively, in parallel.

16. The ultrasonic imaging system as in claim 15, wherein the POST initiates, performs and completes within three seconds of power ON.

17. The ultrasonic imaging system as in claim 15, further comprising:

an extended self-test (EST) performed at the discretion of an operator after completion of the POST, the EST including at least one of the group consisting of a transmit test, a transducer element test, a front end voltage test and a receive test.

18. The ultrasonic imaging system as in claim 15, further comprising:

an extended self-test (EST) performed at the discretion of an operator after completion of the POST, the EST including a transmit test, a transducer element test, a front end voltage test and a receive test.

19. The ultrasonic imaging system as in claim 15, further comprising:

an extended self-test (EST) performed at the discretion of an operator after completion of the POST, the EST including

a transmit test,

a transducer element test which is initiated, performed and completed after completion of the transmit test,

a front end voltage test which is initiated, performed and completed after completion of the transducer element test, and

a receive test which is initiated, performed and completed after completion of the front end voltage test.

20. An ultrasonic imaging system comprising:

a first application specific integrated circuit (ASIC) including a beamformer, first and second built-in pseudo-random number (PRN) generators, and a first built-in cyclic redundancy coding checker, and

a second application specific integrated circuit (ASIC) including a detector and a second built-in cyclic redundancy coding (CRC) checker;

means for initiating, performing and completing a power on self test (POST) for the ultrasonic imaging system within three seconds of power ON, said POST means including a first on-board memory storing run-time code, a second on-board memory having a faster access time than the first on-board memory, wherein the run-time code is configured for performing said POST and ultrasonic scanning, said POST means further including a verification test, the verification test for copying the run-time code from the first on-board memory to the second on-board memory, enabling access to the run-time code from the faster second on-board memory, wherein the verification test is further for verifying that the run-time code has copied correctly; and

means for performing an extended self test (EST) after completion of the POST, wherein a receive digital signal path during ultrasonic scanning passes through the beamformer and then the detector, wherein the POST further includes a receive digital signal path test in which the first PRN generator and first CRC checker operate with the second PRN generator and second CRC checker to test an output of the beamformer and an output of the detector of the receive digital signal path, respectively, in parallel.

21. An ultrasonic imaging system comprising:

a first on-board memory storing run-time code;

a second on-board memory having a faster access time than the first on-board memory;

a first application specific integrated circuit (ASIC) including a beamformer, first and second built-in pseudo-random number (PRN) generators, and a first built-in cyclic redundancy coding checker, and

a second application specific integrated circuit (ASIC) including a detector and a second built-in cyclic redundancy coding (CRC) checker;

a power on self test (POST) which is initiated, performed and completed within three seconds of power ON, the POST including at least one of the group consisting of a verification test, a register test, a controller test, a receive digital signal path test and a basic front end test, wherein the run-time code is configured for performing the POST and ultrasonic scanning, and wherein the verification test is configured for copying the run-time code from the first on-board memory to the second on-board memory, enabling access to the run-time code from the faster second on-board memory, wherein the verification test is further for verifying that the run-time code has copied correctly; and

an extended self-test (EST) performed at the discretion of an operator after completion of the POST, the EST including at least one of the group consisting of a transmit test, a transducer element test, a front end voltage test, and a receive test, further wherein a receive digital signal path during ultrasonic scanning passes through the beamformer and then the detector, wherein the POST further includes a receive digital signal path test in which the first PRN generator and first CRC checker operate with the second PRN generator and second CRC checker to test an output of the beamformer and an output of the detector of the receive digital signal path, respectively, in parallel.