Method and apparatus for SoC design validation

• US 6,678,645 B1
• Filed: 10/28/1999
• Issued: 01/13/2004
• Est. Priority Date: 10/28/1999
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Rajsuman, Rochit, Yamoto, Hiroaki
• Primary Examiner(s): Thomson, W.
• Application Number:
  US09/428,746
• Time in Patent Office: 1,538 Days
• Field of Search: 703/20, 703/21, 703/22, 703/23, 703/24, 703/25, 703/26-28, 703/15, 703/17, 703/19, 703/18, 716/18, 716/4, 716/5, 716/6, 716/16, 716/17, 712/28, 712/35, 714/33, 714/39, 714/735, 714/737, 714/736, 714/741, 714/742
• US Class Current: 703/20
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].

Claims

1. A method for design validation of an embedded cores based SoC (system-on-a-chip) in which a plurality of functional cores are integrated, comprising the following steps of:

producing a plurality of silicon ICs where each silicon IC has a function and circuit structure identical to that of a corresponding core to be integrated into an SoC whose design is validated;

mounting the silicon ICs on a plurality of verification units where each verification unit is a hardware tester and wherein each silicon IC is connected to a corresponding verification unit through a pin electronics having a driver and a comparator;

verifying individual cores to be integrated in the SoC by evaluating performances of the silicon IC corresponding to each core by applying core specific test pattern signals to the silicon IC through the drivers and evaluating resultant outputs from the silicon ICs by the comparators, wherein the core specific test pattern signals are generated with use of simulation testbenches produced through a design stage of the cores;

verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by applying interface test signals therebetween, wherein the interface test signals are generated with use of simulation testbenches developed by an SoC designer and FPGA/emulation of the glue logic;

verifying core-to-core timings and SoC level timing critical paths by evaluating performances of the silicon IC corresponding to each core; and

performing an overall design validation by evaluating overall performances of the plurality of silicon ICs by applying overall performance test pattern signals to the plurality of silicon ICs and evaluating resultant outputs from the silicon ICs where the overall performance test pattern signals are generated with use of simulation testbenches of an overall SoC and application runs.

2. A method for design validation as defined in claim 1, wherein the verifying steps are conducted after assigning a plurality of verification units to the silicon ICs representing the function and structure of the individual cores and mounting the silicon ICs on the corresponding verification units.

3. A method for design validation as defined in claim 1, wherein the verifying steps are conducted after assigning a plurality of verification units to the silicon ICs representing the function and structure of the individual cores and mounting the silicon ICs on the corresponding verification units wherein test pins of the verification units are configured with reference to input/output pins of the silicon ICs under test.

4. A method for design validation as defined in claim 1, wherein the verifying steps are conducted after assigning a plurality of verification units to the silicon ICs representing the function and structure of the individual cores and mounting the silicon ICs on the corresponding verification units wherein each of the verification units is configured as an event based tester which generates the test pattern signals based on event data which describes the test pattern by value changes and their timings extracted from the simulation testbenches.

5. A method for design validation as defined in claim 4, wherein the simulation testbench of the individual cores has an event based data format, thereby facilitating a procedure to generate the test pattern signals for debugging of a fault in the cores of the SoC by the verification unit.

6. A method for design validation of an embedded cores based SoC (system-on-a-chip) in which a plurality of functional cores are integrated, comprising the following steps of:

producing a plurality of silicon ICs each having a function and circuit structure of a corresponding core to be integrated into an SoC;

providing a plurality of verification units and assigning each of the verification units to each of the silicon ICs corresponding to each of the cores;

mounting the silicon ICs on the plurality of verification p units where each verification unit is a hardware tester and wherein each silicon IC is connected to a corresponding verification unit through a pin electronics having a driver and a comparator;

interconnecting the silicon ICs by an interconnect bus modeling an on-chip bus designed in the SoC for connecting between the cores;

verifying the cores to be integrated in the SoC by applying test patterns to the silicon ICs through the drivers and monitoring response output of the silicon ICs by the comparators and the verification units; and

wherein the test patterns are directly produced by using event data in the simulation testbench data produced in a design stage of the cores.

7. A method for design validation as defined in claim 6, further including a step of verifying interface between the silicon ICs representing functions and structures of the cores and glue logic to be integrated in the SoC by emulating the interface and glue logic by an emulator.

8. A method for design validation as defined in claim 6, further including a step of verifying interface between the silicon ICs representing functions and structures of the cores and glue logic to be integrated in the SoC by implementing functions of the interface and glue logic by a field programmable gate array (FPGA).

9. A method for design validation as defined in claim 6, further including a step of verifying core-to-core timings and SoC level timing critical paths by providing test stimulus produced based on SoC level testbench data to the silicon ICs representing functions and structures of the individual cores.

10. A method for design validation as defined in claim 6, further including a step of performing an overall design validation by evaluating an overall performance of the plurality of silicon ICs by applying SoC test patterns to the plurality of silicon ICs, wherein the SoC test patterns are produced with use of simulation testbenches of an overall SoC and application runs.

11. A method for design validation as defined in claim 6, wherein the verifying steps are conducted after assigning a plurality of verification units to the silicon ICs representing functions and structures of the individual cores and mounting the silicon ICs on the corresponding verification units.

12. A method for design validation as defined in claim 6, wherein the verifying steps are conducted after assigning a plurality of verification units to the silicon ICs representing functions and structures of the individual cores and mounting the silicon ICs on the corresponding verification units, wherein each of the verification units is configured as an event based tester which generates a test pattern based on event data which describes the test pattern by value changes and their timings.

13. A method for design validation as defined in claim 12, wherein the simulation testbench of the individual cores has an event based data format, thereby facilitating a procedure to generate the test pattern signals for debugging of a fault in the cores of the SoC by the verification unit.

14. A method for design validation as defined in claim 6, wherein the verifying steps are conducted after assigning a plurality of verification units to the silicon ICs representing functions and structures of the individual cores and mounting the silicon ICs on the corresponding verification units, wherein test pins of the verification units are configured with reference to input/output pins of the silicon ICs under test.

15. An apparatus for design validation of an embedded cores based SoC (system-on-a-chip) in which a plurality of functional cores are integrated, comprising:

a main system computer for interfacing with a user and controlling an overall operation of an apparatus for design validation;

a plurality of verification units which receives testbench data from the main system computer and generates test patterns using the testbench data for testing a plurality of functional cores to be integrated in an SoC by evaluating a plurality of physical silicon ICs produced separately from the functional cores, wherein each of the verification units includes a control computer which receives the testbench data from the main system computer;

a system bus interfacing the main system computer with the plurality of verification units; and

wherein the plurality of silicon ICs are connected to the verification units through pin electronics having drivers and comparators to receive the test pattern from the verification units through the drivers and response outputs of the silicon ICs are evaluated by the comparators and the verification units and main system computer, and wherein each of the silicon ICs has a structure and function identical to that of the corresponding one of the functional cores to be integrated in the SoC.

16. An apparatus for design validation as defined in claim 15, wherein the control computer in each of the verification units produces the test patterns for the silicon IC allocated to the verification unit based on the testbench data from the main system computer through the system bus, applies the test patterns to the silicon IC, and evaluates the response output of the silicon IC, wherein the testbench data are produced through a design stage of the functional cores.

17. An apparatus for design validation as defined in claim 15, wherein each of the verification units is assigned to one of the silicon ICs representing the functional cores.

18. An apparatus for design validation as defined in claim 15, wherein each of the verification units is assigned to one of the silicon ICs representing the functional cores to be integrated in the SoC, and wherein test pins of the verification units are configured with reference to input/output pins of the silicon ICs.

19. An apparatus for design validation as defined in claim 15, wherein each verification unit has a group of test pins, and a pin configuration of the verification unit is freely changed depending on a pin configuration of the silicon IC under test.

20. An apparatus for design validation as defined in claim 15, wherein each verification unit has a group of test pins, and a pin configuration of the verification unit is freely changed depending on a pin configuration of the silicon IC under test, and wherein a size of the group is determined by the main system computer based upon a number of input/output pins of the silicon IC assigned to the verification unit.

21. An apparatus for design validation as defined in claim 15, wherein each of the verification units includes a control computer which receives the testbench data from the main system computer through the system bus and produces the test patterns by extracting event data from the testbench data, applies the test patterns to the silicon IC allocated to the verification unit and evaluates the response output of the silicon IC, and wherein the control computer is provided for each test pin of the verification unit, and wherein the testbench data is produced through a design stage of the functional cores.

22. An apparatus for design validation as defined in claim 15, wherein the verification unit evaluates the assigned silicon IC to verify design integrity of the corresponding functional core, and the verification units further evaluate the interface between the silicon ICs representing the functional cores and glue logic to be integrated in the SoC by emulating the interface and glue logic by an emulator.

23. An apparatus for design validation as defined in claim 15, wherein the verification unit evaluates the assigned silicon IC to verify the corresponding functional core, and the verification units further evaluate the interface between the silicon ICs representing the functional cores and glue logic to be integrated in the SoC by implementing functions of the interface and glue logic by a field programmable gate array (FPGA).

24. An apparatus for design validation as defined in claim 15, wherein the main system computer and the verification units verify core-to-core timings and SoC level timing critical paths by applying test stimulus produced based on SoC level testbench data to the silicon ICs representing the functions and structures of the individual cores.

25. An apparatus for design validation as defined in claim 15, wherein the main system computer and the verification units verify an overall SoC design by evaluating an overall performance of the plurality of silicon ICs with use of simulation testbenches of an overall SoC and application runs.

26. An apparatus for design validation as defined in claim 15, wherein the main system computer and the verification units verify an overall SoC design by evaluating an overall performance of the plurality of silicon ICs with use of simulation testbenches of an overall SoC and application runs, and wherein the main system computer distributes partition SoC software application computations to the verification units by breaking the computations into multiple sub-tasks and assigning the sub-tasks in a distributed fashion on the plurality of verification units.

27. An apparatus for design validation as defined in claim 15, wherein the main system computer and the verification units verify an overall SoC design by evaluating an overall performance of the plurality of silicon ICs with use of simulation testbenches of an overall SoC and application runs, and wherein the main system computer distributes partition SoC software application computations to the verification units by breaking the computations into multiple sub-tasks and assigning the sub-tasks in a distributed fashion on the plurality of verification units, and wherein the main computer combines responses of the silicon ICs from the verification units to form an SoC level response to determine any error/failure.

28. An apparatus for design validation as defined in claim 15, further including a performance board which mounts the corresponding silicon IC thereon in each of the verification units.

29. An apparatus for design validation as defined in claim 15, further including a performance board which mounts all of the silicon ICs and glue logic under test.

30. An apparatus for design validation as defined in claim 15, wherein each of the verification units is configured as an event based tester which generates the test pattern based on event data which describes the test pattern solely by value changes and their timings.

31. An apparatus for design validation as defined in claim 30, wherein the simulation testbench of the individual cores has an event based data format, thereby facilitating a procedure to generate the test pattern signals for debugging of a fault in the cores of the SoC by the verification unit.

32. An apparatus for design validation as defined in claim 15, wherein each of the verification units is configured as an event based tester which is comprised of:

an event memory for storing timing data of each event formed where the timing data is formed with an integer multiple of a reference clock period (integral part data) and a fraction of the reference clock period (fractional part data), the timing data being a time difference between a current event and a predetermined reference point;

an address sequencer for generating address data for accessing the event memory;

an event count logic for generating an event start signal which is determined by the reference clock period and a sum of the integral part data;

an event generation unit for generating each event based on the event start signal from the event count logic and the fractional part data for formulating the test pattern; and

a pin unit write decoder for detecting an address of a verification unit for assigning the verification unit to the pins of the silicon IC.

33. An apparatus for design validation of an embedded cores based SoC (system-on-a-chip) in which a plurality of functional cores are integrated, comprising:

a main system computer for interfacing with a user and controlling an overall operation of an apparatus for design validation;

a plurality of verification units which receives testbench data from the main system computer and generates test patterns using the testbench data for testing a plurality of functional cores to be integrated in an SoC by evaluating a plurality of physical silicon ICs produced separately from the functional cores;

a system bus interfacing the main system computer with the plurality of verification units;

wherein the plurality of silicon ICs are connected to the verification units through pin electronics having drivers and comparators to receive the test pattern from the verification units through the drivers and response outputs of the silicon ICs are evaluated by the comparators and the verification units and main system computer, and wherein each of the silicon ICs has a structure and function identical to that of the corresponding one of the functional cores to be integrated in the SoC; and

wherein the main system computer performs all tasks of generating test patterns to be supplied to the silicon ICs, evaluating response outputs of the silicon ICs, conducting timing and interface evaluation of the SoC, and an overall design validation of the SoC.