Interprocessor communication system for parallel processing

• US 6,678,722 B1
• Filed: 05/11/2000
• Issued: 01/13/2004
• Est. Priority Date: 05/14/1999
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kanoh, Yasushi
• Primary Examiner(s): CALDWELL, ANDREW T
• Application Number:
  US09/568,593
• Time in Patent Office: 1,342 Days
• Field of Search: 709/212-216, 710/22-28, 711/202-210, 711/156, 712/28-31
• US Class Current: 709/212
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]

Abstract

The present invention is directed to providing an interprocessor communication system capable of obviating degradation of the performance in an interprocessor communication caused by the processing to avoid a page fault. In this system, a source processor transmits a check packet directly after successive data is transmitted by the interprocessor communication, to confirm whether or not a page fault takes place on the receiver side. The source processor carries out no processing in the case that no page fault takes place, and, in the case that a page fault takes place, the data in the page-faulty page is retransmitted. The destination processor stores the logical page numbers of the page-faulty pages in the main memory to utilize the data retransmission. Furthermore, the destination processor confirms whether or not the page faults occur in the identical page and if that is the case, no interrupt is raised so as to avoid too frequent interrupts.

Claims

1. An interprocessor communication system for a parallel-computer system with plural processors combined through a network, each of said processors having a CPU, a main memory, a transmitter device and a receiver device, and communicating with other processors by means of an interprocessor communication with a read address and a write address designated in terms of a logical address, each of said processors including:

a translation means provided in each of said transmitter device and said receiver device for translating a logical address to a physical address; and

a buffer means provided in a position on said main memory for storing specific information concerning a fault-page, said position being determined both by a communication ID assigned to each task and by a source logical processor number for a packet to be sent, said buffer means comprising;

a flag section for storing flag information indicating an occurrence of the page fault during the interprocessor communication from a source logical processor to the task to which the communication ID is assigned;

a field for entering the logical page number information of a page in which the latest page-fault takes place;

a field for entering the number of logical pages in which page faults take place during the interprocessor communication concerned; and

a field for entering an address information that indicates an area to store the logical page numbers of page-faulty logical pages.

2. An apparatus as claimed in claim 1, wherein said main memory is further provided with a fault-page list for storing said logical page numbers of page-faulty logical pages, and wherein if the address translation made by said translation means in said receiver device results in a physical page being in a state of page-out, then the data concerning the result of the address translation is stored in said flag section, said field for entering the logical page number information, said field for entering the number of logical pages and said field for entering an address information.

3. An apparatus as claimed in claim 2, wherein if the result of said address translation indicates the state of a page indicative of page-out, the logical page subjected to said address translation is assigned to a dummy physical page designated beforehand.

4. An interprocessor communication system as claimed in claim 2, wherein said translation means has, as information of a logical page that constitutes a part of a logical address, a number of the physical page assigned to the logical page and the state of the physical page, said state of the physical page being defined to come in any of the following specific states of page:

(i) the state of “

invalid”

in which the translated physical page is not allocated to the main memory;

(ii) the state of “

page out”

in which the translated physical page is currently absent in the main memory and is paged out to an external storing medium;

(iii) the state of “

on paging-in”

in which the translated physical page was previously in the state of “

page out” and

is currently on page-in processing;

(iv) the state of “

page in”

in which the translated physical page is now allocated to the main memory.

5. An interprocessor communication system as claimed in claim 4, wherein said translation means has entries of communication IDs, logical page numbers of logical pages, the physical page numbers of the physical pages assigned to the logical pages and the states of the physical pages, and is provided with a first comparison means for comparing the communication ID and logical page to be translated with the communication IDs and logical page numbers, respectively, in the entries to provide outputs of the physical page number corresponding to the logical page number of the logical page to be translated and also the state of the physical page.

6. An interprocessor communication system as claimed in claim 5, wherein said receiver device is provided with a second comparison means for comparing the logical page number to be translated with the logical page number entered in said buffer means to judge whether or not the logical page number of concern coincides with the logical page number of the latest page-faulty logical page, and wherein in the case that said translation means indicates, as the state of the physical page assigned to the logical page of concern, the state of “

on page-in processing”

;

if said second comparison means judges to be coincident, then said receiver device performs no processing; and

if said second comparison means judges to be incoincident, then said receiver device raises an interrupt in order to ask the OS to add said logical page number of concern to said fault-page list to store the logical page number of concern as the latest page-faulty logical page and to increase the number of the page-faulty page in said buffer means by 1.

7. A system as claimed in claim 1, wherein the source processor transmits a check packet after one parcel is transmitted, the parcel header of said check packet having a format including a field to enter a swapping data and also a field to enter a write address for a reply packet in reply to said check packet, and wherein the destination processor, when receiving the check packet, swaps said swapping data with the entry of said buffer means to provide a reply to said check packet and returns said reply to said source processor to store said entry of the buffer means in the area of said main memory designated by said write address.

8. A system as claimed in claim 7, wherein said source processor has a means for checking whether or not a page fault takes place on the receiver side of the interprocessor communication in the latest data that has been transmitted from the source processor.

9. A system as claimed in claim 8, wherein said source processor reads said fault-page list by means of a remote read packet, said fault-page list storing the logical page numbers of the page-faulty logic pages successively entered when the page fault occurs during the interprocessor communication of concern, and retransmits exclusively the data of the logical page numbers entered in the fault-page list.

10. A system as claimed in claim 9, wherein after the retransmission, said source processor confirms presence or absence of a page fault by said packet and repeats the retransmission until said processor confirms absence of the page fault.