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Interprocessor communication system for parallel processing

  • US 6,678,722 B1
  • Filed: 05/11/2000
  • Issued: 01/13/2004
  • Est. Priority Date: 05/14/1999
  • Status: Active Grant
First Claim
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1. An interprocessor communication system for a parallel-computer system with plural processors combined through a network, each of said processors having a CPU, a main memory, a transmitter device and a receiver device, and communicating with other processors by means of an interprocessor communication with a read address and a write address designated in terms of a logical address, each of said processors including:

  • a translation means provided in each of said transmitter device and said receiver device for translating a logical address to a physical address; and

    a buffer means provided in a position on said main memory for storing specific information concerning a fault-page, said position being determined both by a communication ID assigned to each task and by a source logical processor number for a packet to be sent, said buffer means comprising;

    a flag section for storing flag information indicating an occurrence of the page fault during the interprocessor communication from a source logical processor to the task to which the communication ID is assigned;

    a field for entering the logical page number information of a page in which the latest page-fault takes place;

    a field for entering the number of logical pages in which page faults take place during the interprocessor communication concerned; and

    a field for entering an address information that indicates an area to store the logical page numbers of page-faulty logical pages.

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