Apparatus and method for a personal computer system providing non-distracting video power management

• US 6,678,834 B1
• Filed: 03/16/1999
• Issued: 01/13/2004
• Est. Priority Date: 03/20/1998
• Status: Expired due to Fees

• Current Assignee: Videocon Global Ltd. (Videocon Industries Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Kamijo, Noboru, Sekiya, Kazuo, Shimotono, Susumu, Ishikawa, Hiroshi, Furuichi, Sanehiro, Aihara, Toru
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/270,416
• Time in Patent Office: 1,764 Days
• Field of Search: 713/300, 713/322, 713/324, 713/500, 713/501, 345/87, 345/89, 345/98, 345/212
• US Class Current: 713/501
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

To change the frequency of a video clock without adversely affecting a display quality. To lower the frequency of a video clock, following steps are executed, detecting an opportunity which causes the reduction of the frequency of the video clock; lowering the frequency of the video clock in a frequency range within which a circuit employing the video clock (for example, a PLL (Phase Lock Loop) circuit) can follow a change in the frequency; and iterating the step of lowering the frequency of the video clock until a predetermined frequency is attained. In addition, the following steps are also performed, detecting an opportunity which causes the reduction of the frequency of the video clock; lowering the frequency of the video clock to a predetermined frequency during a vertical blanking interval of a display device that employs the video clock; and maintaining the predetermined frequency of the video clock until change of the frequency is required. Furthermore, the following steps are performed, detecting an opportunity which causes the reduction of the frequency of the video clock; changing a display color on a screen of a display device to a color for which flickers are not outstanding; and lowering the frequency of the video clock.

Claims

1. A method for use with a computer display system having an LCD display with a driver having a phase lock loop timed by a video clock of adjustable frequency, said method comprising the steps of:

detecting an opportunity which is preselected to initiate a reduction of the frequency of the video clock;

lowering the frequency of the video clock in a frequency increment selected to be within a range for which the phase-lock circuit employing the video clock can follow such change in the frequency without loss of stability; and

iterating the step of lowering the frequency of the video clock, at least once, until a predetermined frequency is attained.

2. The method according to claim 1, wherein the opportunity which causes the reduction of the video clock is detected in accordance with the type of application whose window is displayed on a screen of the LCD display device.

3. The method of claim 1 wherein said frequency increments are selected to be less than 5% of the video clock frequency whereby destabilization of the phase lock loop is avoided.

4. A computer having a LCD display device and a driver which provides an interval between display refreshes and includes a phase-lock circuit which responds to a video clock signal having an adjustable frequency, comprising:

signal logic for detecting an operating system execution of certain preselected application programs known to present opportunities for low video activity and signaling such low video activity opportunities; and

a controller for lowering the frequency of the video clock to a predetermined frequency during said interval in multiple sub-increments of frequency of a size selected to allow the phase-lock circuit to follow without destabilizing, and for maintaining the predetermined frequency of the video clock until said signal logic signals a change of video activity.

5. The computer of claim 4 wherein said sub-increments are of a size less than 5% of the video clock frequency.