Distributed interface for parallel testing of multiple devices using a single tester channel
First Claim
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1. A probe card assembly comprising:
- a plurality of electrical contacts configured to make electrical connections with a semiconductor tester;
a plurality of probes disposed to contact a plurality of semiconductor devices to be tested; and
interface circuitry comprising;
receiving circuitry configured to receive from said semiconductor tester through ones of said electrical contacts test data, a location in one of said semiconductor devices, and expected response data;
writing circuitry configured to write through ones of said probes copies of said test data to said location in at least two of said plurality of semiconductor devices; and
reading circuitry configured to read through ones of said probes actual response data generated by each of said at least two of said semiconductor devices in response to said test data.
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Abstract
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.
174 Citations
20 Claims
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1. A probe card assembly comprising:
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a plurality of electrical contacts configured to make electrical connections with a semiconductor tester;
a plurality of probes disposed to contact a plurality of semiconductor devices to be tested; and
interface circuitry comprising;
receiving circuitry configured to receive from said semiconductor tester through ones of said electrical contacts test data, a location in one of said semiconductor devices, and expected response data;
writing circuitry configured to write through ones of said probes copies of said test data to said location in at least two of said plurality of semiconductor devices; and
reading circuitry configured to read through ones of said probes actual response data generated by each of said at least two of said semiconductor devices in response to said test data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
an interface board on which said electrical contacts are disposed; and
a space transformer on which said probes are disposed.
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6. The probe card assembly of claim 5, wherein at least one of said receiving circuitry, said writing circuitry, and said reading circuitry is disposed on said space transformer.
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7. The probe card assembly of claim 5, wherein said receiving circuitry, said writing circuitry, and said reading circuitry compose one or more integrated circuit chips.
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8. The probe card assembly of claim 7, wherein each of said one or more integrated circuit chips is disposed on said space transformer.
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9. The probe card assembly of claim 8, wherein said plurality of probes is disposed on a first surface of said space transformer, and each of said one or more integrated circuit chips is disposed on a second surface of said space transformer.
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10. The probe card assembly of claim 9, wherein said first surface of said space transformer is opposite said second surface of said space transformer.
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11. The probe card assembly of claim 1, wherein said plurality of probes is configured to contact said plurality of semiconductor devices while said semiconductor devices are in unsingulated wafer form.
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12. A probe card assembly comprising:
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tester interface means for making electrical connections with a semiconductor tester;
probe means for contacting a plurality of semiconductor devices to be tested;
receiving means for receiving through said tester interface means test data, a location in one of said semiconductor devices, and expected response data;
writing means for writing through said probe means copies of said test data to said location in at least two of said plurality of semiconductor devices; and
reading means for reading through said probe means actual response data generated by each of said at least two of said semiconductor devices in response to said test data. - View Dependent Claims (13, 14, 15)
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16. A method of testing a plurality of semiconductor devices comprising:
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generating at a semiconductor tester test data and location data identifying a location on one of said semiconductor devices;
transmitting said test data and said location data to a probe card assembly;
writing said test data from said probe card assembly to said location on at least two of said semiconductor devices;
generating at said semiconductor tester expected response data;
transmitting said expected response data to said probe card assembly; and
reading at said probe card assembly actual response data from each of said at least two of said semiconductor devices. - View Dependent Claims (17, 18, 19, 20)
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Specification