Delay calculation method and design method of a semiconductor integrated circuit
First Claim
1. A delay calculation method of a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires, in which a circuit connected to the output pin of an electronic circuit cell is replaced by one effective capacitance to calculate a delay in said electronic circuit cell, comprising:
- a procedure which inputs a load parameter in which a circuit connected to said output pin is expressed by an equivalent circuit including resistance and capacitance or inductance;
a procedure which calculates transition time until the voltage of said output pin reaches a definition voltage for delay;
a procedure which calculates voltage of capacitance node of said equivalent circuit at said transition time;
a procedure which calculates said effective capacitance from the voltage of said capacitance node; and
a procedure which calculates a delay in said electronic circuit cell from said effective capacitance.
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Accused Products
Abstract
There is provided a delay calculation method considering a shield effect applicable to delay calculation for a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires.
A method for replacing a circuit connected to the output pin of an electronic circuit cell by one effective capacitance to calculate a delay in the electronic circuit cell, comprising procedure (111) which inputs a load parameter in which a circuit connected to the output pin is expressed by an equivalent circuit including resistances and capacitances or inductances, procedure (101) which calculates voltage of capacitance node of the equivalent circuit at transition time until the voltage of the output pin reaches a definition voltage for delay, procedure (103) which calculates the effective capacitance from the voltage of the capacitance node, and procedure (104) which calculates a delay (112) in the electronic circuit cell from the effective capacitance.
This can calculate a delay in a semiconductor integrated circuit fast with high accuracy.
14 Citations
13 Claims
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1. A delay calculation method of a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires, in which a circuit connected to the output pin of an electronic circuit cell is replaced by one effective capacitance to calculate a delay in said electronic circuit cell, comprising:
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a procedure which inputs a load parameter in which a circuit connected to said output pin is expressed by an equivalent circuit including resistance and capacitance or inductance;
a procedure which calculates transition time until the voltage of said output pin reaches a definition voltage for delay;
a procedure which calculates voltage of capacitance node of said equivalent circuit at said transition time;
a procedure which calculates said effective capacitance from the voltage of said capacitance node; and
a procedure which calculates a delay in said electronic circuit cell from said effective capacitance. - View Dependent Claims (2, 8, 10, 12)
a delay calculation procedure which calculates a delay in said electronic circuit cell, a judgment procedure which judges whether desired conditions are met, and a cell modification procedure which modifies the type or a combination of said electronic circuits, in which the type or a combination of said electronic circuit cells is selected so as to meet the desired conditions, the design method comprising using the delay calculation method according to claim 1 as said delay calculation procedure.
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12. A recording medium which records a program for processing the delay calculation method according to claim 1.
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3. A delay calculation method of a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires, in which a circuit connected to the output pin of an electronic circuit cell is replaced by one effective capacitance to calculate a delay in said electronic circuit cell, comprising:
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a procedure which inputs a load parameter in which a circuit connected to said output pin is expressed by an equivalent circuit including resistances and capacitances or inductances;
a procedure which calculates output transition time until the voltage of said output pin reaches a definition voltage for delay;
a procedure which calculates capacitance node transition time until voltage of capacitance node of said equivalent circuit reaches said definition voltage for delay;
a procedure which calculates said effective capacitance from said output transition time and said capacitance node transition time; and
a procedure which calculates a delay in said electronic circuit cell from said effective capacitance. - View Dependent Claims (4, 5, 6, 7, 9, 11, 13)
a delay calculation procedure which calculates a delay in said electronic circuit cell, a judgment procedure which judges whether desired conditions are met, and a cell modification procedure which modifies the type or a combination of said electronic circuits, in which the type or a combination of said electronic circuit cells is selected so as to meet the desired conditions, the design method comprising using the delay calculation method according to claim 3 as said delay calculation procedure.
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13. A recording medium which records a program for processing the delay calculation method according to claim 3.
Specification
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- Resources
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsOhkubo, Norio
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Primary Examiner(s)Smith, Matthew
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Assistant Examiner(s)LIN, SUN J
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Application NumberUS09/925,382Publication NumberTime in Patent Office886 DaysField of Search716/6, 716/1-18US Class Current716/113CPC Class CodesG06F 30/33 Design verification, e.g. f...
