Space efficient interconnect test multi-structure

• US 6,680,484 B1
• Filed: 10/22/2002
• Issued: 01/20/2004
• Est. Priority Date: 10/22/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Young, Bradley Scott
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US10/277,265
• Time in Patent Office: 455 Days
• Field of Search: 257/48
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

The present invention relates to a test structure and a method for forming a test structure over a semiconductor substrate. The test structure comprises a plurality of patterned electrically conductive metal layers within a scribe line. The plurality of metal layers further comprises one or more lower metal layers comprising a plurality of split pads longitudinally spaced along the length of the scribe line, wherein a channel traversing the length of the scribe line is define. One or more top metal layers comprising a plurality of solid pads generally residing over the split pads defines a plurality of columns of pads. One or more conduits generally residing within the channel are associated with one or more lower metal layers and connect two or more split pads associated with the respective one or more lower metal layers, wherein a bow-tie lead is defined. One or more insulating layers are further disposed between the plurality of metal layers, and a plurality of pad vias electrically connect the respective split pads and solid pads associated with the respective two or more columns of pads.

Claims

1. A test structure formed over a semiconductor substrate within a scribe line, the scribe line having a length and width associated with a surface of the substrate and a height associated with a distance from the surface of the substrate, the test structure comprising:

a plurality of patterned electrically conductive metal layers formed over the substrate and spaced along the height of the scribe line, the plurality of metal layers further comprising;

one or more lower metal layers formed over the substrate, the one or more lower metal layers comprising a plurality of split pads longitudinally spaced along the length of the scribe line, the split pads each comprising two pad portions oppositely disposed from one another and separated by a predetermined distance, thereby defining a channel between the plurality of split pads, wherein the channel traverses the length of the scribe line;

a top metal layer formed over the one or more lower metal layers, the top metal layer comprising a plurality of solid pads longitudinally spaced along the length of the scribe line by a predetermined distance, wherein two or more of the plurality of solid pads generally reside over the plurality of split pads, thereby defining a respective plurality of columns of pads, wherein the plurality of columns of pads are spaced along the length of the scribe line in accordance with the spacing of the plurality of solid pads; and

one or more longitudinal conduits associated with one or more lower metal layers, wherein the one or more conduits electrically connect two or more split pads associated with the respective one or more lower metal layers, wherein the one or more conduits generally reside within the channel, and wherein at least one of the one or more conduits is characterized by a first width and a second width, wherein the first width is larger than the second width, thereby defining a bow-tie lead;

one or more insulating layers disposed between the plurality of metal layers; and

a plurality of pad vias, wherein the plurality of pad vias electrically connect the respective split pads and solid pads associated with the respective two or more columns of pads.

2. The test structure of claim 1, comprising two or more conduits associated with two or more lower metal layers, the test structure further comprising one or more electrically conductive lead vias, wherein the one or more lead vias extend between the two or more conduits associated with the two or more respective metal layers, electrically connecting the two or more conduits therein.

3. The test structure of claim 1, wherein each of the plurality of columns are longitudinally spaced from one another by a predetermined distance.

4. The test structure of claim 1, wherein a length of the second width of the bow-tie lead is between 200 microns and 1000 microns.

5. The test structure of claim 1, comprising two or more bow-tie leads residing on two or more respective metal layers, wherein a cross-sectional area at the respective first width and second width of each conduit is generally equal across the plurality of metal layers.

6. The test structure of claim 1, further comprising one or more longitudinal top conduits associated with the top metal layer, wherein the one or more top conduits electrically connect two or more solid pads associated with the top metal layer, wherein the one or more top conduits generally reside adjacent to two or more solid pads, and wherein at least one of the one or more top conduits is characterized by a first width and a second width, wherein the first width is larger than the second width, thereby defining a top layer bow-tie lead.

7. The test structure of claim 6, wherein a length of the second width of the top layer bow-tie lead is between 200 and 1000 microns.

8. The test structure of claim 1, wherein the two or more split pads electrically connected by the one or more conduits are separated by at least a length of four split pads.

9. The test structure of claim 1, wherein the solid pads are characterized by a length and width which is larger than a pin associated with a test card, wherein two or more solid pads are operable to be electrically contacted by two or more pins of a test card, and wherein a plurality of pins associated with the test card.

10. The test structure of claim 1, wherein a length and width of each solid pad is between 50 and 70 microns.

11. The test structure of claim 1, wherein the width of the scribe line is less than approximately 78 microns.

12. The test structure of claim 1, wherein the predetermined distance separating the two pad portions oppositely disposed from one another is less than 10 microns.

13. The test structure of claim 1, wherein the solid pads and split pads comprise a metal selected from the group consisting of tungsten, copper, and aluminum.

14. The test structure of claim 1, wherein the solid pads and split pads comprise a plurality of patterned oxide reinforcement members.

15. The test structure of claim 1, wherein one or more of the lower metal layers further comprises one or more electrically conductive extrusion monitors laterally spaced a predetermined distance from one or more bow-tie leads associated with the respective lower metal layer, wherein a portion the one or more extrusion monitors generally reside about a periphery of one or more respective bow-tie leads and are electrically connected to one or more of the split pads, and wherein the one or more extrusion monitors are operable to detect a short circuit condition between the extrusion monitor and the respective bow-tie lead.

16. The test structure of claim 1, wherein the semiconductor substrate comprises one or more doped regions, wherein one or more split pads associated with a lower metal layer closest to the surface of the semiconductor substrate is electrically connected to the one or more respective doped regions by one or more pad vias.

17. The test structure of claim 16, wherein the one or more doped regions comprise one or more doped polysilicon moats.

18. The test structure of claim 1, comprising two lead vias electrically connected to two of the plurality of lower metal layers, wherein the two lead vias are operable to be utilized as a Van der Pauw leads.

19. The test structure of claim 1, comprising twenty solid pads and five metal layers, wherein one or more of the five metal layers proximate to the surface of the semiconductor substrate comprise signal leads.

20. The test structure of claim 1, comprising two or more top metal layers, wherein one or more lower metal layers reside over at least one of the top metal layers.