Semiconductor build-up package

• US 6,680,529 B2
• Filed: 02/15/2002
• Issued: 01/20/2004
• Est. Priority Date: 02/15/2002
• Status: Expired due to Term

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Ding, Yi-Chuan, Ou, In-De, Chen, Kun-Ching
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/075,227
• Publication Number:
  US 20030157747A1
• Time in Patent Office: 704 Days
• Field of Search: 257/700, 257/690, 257/723, 257/734, 257/737, 257/778, 257/779, 257/780, 257/784, 257/783
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Claims

1. A semiconductor build-up package comprising:

a die having an active surface with a plurality of contacts and an inactive surface;

a circuit board having a first surface, a second surface and a plurality of conductive traces, the circuit board being a multi-layer printed circuit board, wherein the first surface has a cavity for accommodating the die; and

a first dielectric layer formed on the active surface of the die and the first surface of the circuit board, having a plurality of conductive columns, wherein at least a conductive column is electrically coupled to the conductive traces of the circuit board.

2. The semiconductor build-up package in accordance with the claim 1, further comprising at least a second dielectric layer formed on the first dielectric layer, the second dielectric layer having a plurality of conductive columns.

3. The semiconductor build-up package in accordance with the claim 2, wherein at least a conductive column of the second dielectric layer is vertically bonded on the corresponding conductive column of the first dielectric layer.

4. The semiconductor build-up package in accordance with the claim 1, wherein the first surface of the circuit board is coplanar to the active surface of the die.

5. The semiconductor build-up package in accordance with the claim 1, wherein the circuit board includes resistances, condensers or fuses inside.

6. The semiconductor build-up package in accordance with the claim 1, wherein the die is adhered at the cavity.

7. The semiconductor build-up package in accordance with the claim 2, further comprising solder balls, bumps or pins formed on the second dielectric layer.

8. The semiconductor build-up package in accordance with the claim 1, wherein the conductive column of the first dielectric layer is vertically bonded on the first surface of the circuit board.

9. The semiconductor build-up package in accordance with the claim 1, further comprising a second die on the second surface of the circuit board.

10. The semiconductor build-up package in accordance with the claim 9, further comprising a plurality of bonding wires electrically connecting the second die with the circuit board.

11. The semiconductor build-up package in accordance with the claim 9, further comprising flip chip bumps electrically connecting the second die with the circuit board.

12. A semiconductor multi-chip package comprising:

at least a first die having an active surface, and inactive surface and a plurality of contacts on the active surface;

a circuit board having a first surface, a second surface, a cavity formed on the first surface for accommodating the first die, wherein there are a plurality of conductive traces inside the circuit board;

a first dielectric layer formed on the active surface of the first die and the first surface of the circuit board, the first dielectric layer having a plurality of conductive columns, wherein at least a conductive column electrically connects with the conductive traces of the circuit board; and

at least a second die mounted on the second surface of the circuit board, the second die having a plurality of contacts which are electrically coupled to the conductive traces of the circuit board.

17. The semiconductor multi-chip package in accordance with the claim 12, wherein the first surface of the circuit board is coplanar to the active surface of the first die.

18. The semiconductor multi-chip package in accordance with the claim 12, wherein the circuit board is a multi-layer printed circuit board.

19. The semiconductor multi-chip package in accordance with the claim 12, further comprising an encapsulating material on the second surface of the circuit board.

13. The semiconductor multi-chip package in accordance with the claim 13, further comprising at least a second dielectric layer lying on the first dielectric layer, the second dielectric layer having a plurality of conductive columns.

14. The semiconductor multi-chip package in accordance with the claim 13, wherein at least a conductive column of the second dielectric layer is vertically bonded on the corresponding conductive column of the first dielectric layer.

15. The semiconductor multi-chip package in accordance with the claim 13, further comprising a circuit layer between the first dielectric layer and the second dielectric layer for electrically connecting with the conductive columns.

16. The semiconductor multi-chip package in accordance with the claim 13, further comprising solder balls, bumps or pins formed on the second dielectric layer.