Semiconductor device and process for producing the same

• US 6,680,541 B2
• Filed: 01/18/2002
• Issued: 01/20/2004
• Est. Priority Date: 01/18/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Yoneyama, Ryou, Ryuzaki, Daisuke, Furusawa, Takeshi, Sakuma, Noriyuki, Machida, Shuntaro, Hinode, Kenji
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Dolan, Jennifer M.
• Application Number:
  US10/050,859
• Publication Number:
  US 20020105085A1
• Time in Patent Office: 732 Days
• Field of Search: 257/759, 257/642, 257/40, 438/623, 438/780, 438/781, 438/82, 438/99
• US Class Current: 257/759
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.

Claims

1. A semiconductor device including one or more intermetal insulating films, each intermetal insulating if film containing at least silicon atoms, oxygen atoms, and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage of 14% or has in the film thickness direction at a time of oxidation, said shrinkage being measured after treating a surface of the film with an oxygen-plasma treatment under a pressure of 1 torr or more so as to decompose organic components below the film surface exposed to the treatment.

2. A semiconductor device according to claim 1, wherein the shrinkage in the film thickness direction at the time of oxidation is 10% or less.

3. A semiconductor device according to claim 1, wherein the intermetal insulating film has a relative dielectric constant of 3.5 or less.

4. A semiconductor device according to claim 1, wherein the intermetal insulating film has all of Si—

CH₃ bond, Si—

O—

Si bond and Si—

C—

Si bond.

5. A semiconductor device including one or more wiring layers, each layer having a plurality of inlaid wires and intermetal insulating films between individual inlaid wires, said intermetal insulating film being a single layer film of a low dielectric constant film having a dielectric constant lower than that of a silicon oxide film, said low dielectric constant film having a shrinkage of 14% or less in the film thickness direction at a time of oxidation, said shrinkage being measured after treating a surface of the film with an oxygen-plasma treatment under a pressure of 1 torr or more so as to decompose organic components below the film surface exposed to the treatment,

wherein the low dielectric constant film contains at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2.

6. A semiconductor device according to claim 5, wherein the shrinkage in the film thickness direction at the time of oxidation is 10% or less.

7. A semiconductor device including one or more wiring layers, each layer having a plurality of inlaid wires and intermetal insulating films between individual inlaid wires, said intermetal insulating film being a stack of a plurality of insulating films, the uppermost insulating film being a low dielectric constant film having a dielectric constant lower than that of a silicon oxide film, said low dielectric constant film having a shrinkage of 14% or less in the film thickness direction at a time of oxidation, said shrinkage being measured after treating a surface of the film with an oxygen-plasma treatment under a pressure of 1 Torr or more so as to decompose organic components below the film surface exposed to the treatment,

wherein the low dielectric constant film contains at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2.

8. A semiconductor device according to claim 7, wherein the shrinkage in the film thickness direction at the time of oxidation is 10% or less.