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Method/architecture for a low gain PLL with wide frequency range

  • US 6,680,632 B1
  • Filed: 02/26/2002
  • Issued: 01/20/2004
  • Est. Priority Date: 02/26/2002
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a voltage controlled oscillator (VCO) within a phase lock loop (PLL) configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input, wherein (i) said low gain control input and said high gain control input are both active and (ii) a filter circuit that is configured to clamp said low gain control input in response to reaching a maximum operating point prior to said PLL acquiring a lock.

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