Method/architecture for a low gain PLL with wide frequency range

• US 6,680,632 B1
• Filed: 02/26/2002
• Issued: 01/20/2004
• Est. Priority Date: 02/26/2002
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Meyers, Steven, Moyal, Nathan Y.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/083,442
• Time in Patent Office: 693 Days
• Field of Search: 327/155, 327/156, 327/157, 327/147, 327/148, 327/146, 331/17, 331/25, 331/34, 331/187, 331/DIG.2, 331/179, 331/180, 375/294, 375/375, 375/376
• US Class Current: 327/155
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/102 the additional signal being directly applied to the controlled loop oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An apparatus comprising a voltage controlled oscillator (VCO) within a phase lock loop (PLL) that may be configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input. The low gain control input and the high gain control input are generally both active.

Claims

1. An apparatus comprising:

a voltage controlled oscillator (VCO) within a phase lock loop (PLL) configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input, wherein (i) said low gain control input and said high gain control input are both active and (ii) a filter circuit that is configured to clamp said low gain control input in response to reaching a maximum operating point prior to said PLL acquiring a lock.

2. The apparatus according to claim 1, wherein said PLL further responds to an input signal.

3. The apparatus according to claim 1, wherein said high gain control input is generated in further response to an operational amplifier circuit.

4. The apparatus according to claim 3, wherein said amplifier circuit is configured to generated said high gain input in response to (i) a reference signal and (ii) said low gain input.

5. The apparatus according to claim 1, wherein said high gain control input comprises a low bandwidth input and said low gain control input comprises a high bandwidth input.

6. The apparatus according to claim 3, wherein said filter circuit comprises a very low bandwidth low pass filter.

7. The apparatus according to claim 1, wherein said PLL comprises a dual filter configured to generate said low gain control input and said high gain control input in response to a pump output.

8. The apparatus according to claim 1, wherein said high gain control input is generated in response to (i) a low bandwidth filter circuit and (ii) said low gain control input.

9. The apparatus according to claim 1, wherein said high gain control input is generated in response to a number of amplifiers and filter circuits.

10. The apparatus according to claim, 3, wherein said amplifier is configured to generate said high gain input by filtering said input signal.

11. The apparatus according to claim 4, wherein said reference signal comprises a frequency approximately at a midpoint of an operating frequency range of said PLL.

19. The apparatus according to claim 1, further comprising an amplifier having (i) a first input coupled to said low gain control input and (ii) a second input coupled to an external signal.

20. The apparatus according to claim 19, wherein said external signal comprises a frequency range reference signal.

12. An apparatus for operating a voltage controlled oscillator (VCO) within a phase lock loop (PLL) comprising:

means for receiving a low gain control signal;

means for receiving a high gain control signal; and

means for generating an output signal having a frequency in response to said low gain and high gain control signals, wherein (i) said low gain control signal and said high gain control signal are both active and (ii) a filter circuit is configured to clamp said low gain control signal in response to reaching a maximum operating point prior to said PLL acquiring a lock.

13. A method for operating a voltage controlled oscillator (VCO) within a phase lock loop (PLL) comprising the steps of:

(A) receiving a low gain control signal;

(B) receiving a high gain control signal; and

(C) generating an output signal having a frequency in response to said low gain and high gain control signals, wherein (i) said low gain control signal and said high gain control signal are both active and (ii) a filter circuit is configured to clamp said low gain control signal in response to reaching a maximum operating point prior to said PLL acquiring a lock.

14. The method according to claim 13, wherein said method comprises:

generating said low gain control signal and said high gain control signal in response to a pump output via dual filter.

15. The method according to claim 13, wherein said method further comprises the step of:

generating said low gain and high gain control signals continuously.

16. The method according to claim 13, wherein step (C) further comprises said high gain control input after a startup condition.

17. The method according to claim 13, wherein said method comprises generating said high gain control signal in response to an operational amplifier circuit and a filter circuit.

18. The method according to claim 13, wherein said method comprises generating said high gain control signal by filtering a reference signal.