Methods and apparatus for accurate phase detection

• US 6,680,691 B2
• Filed: 05/13/2002
• Issued: 01/20/2004
• Est. Priority Date: 05/13/2002
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Burlet, Todd R., Hager, James R., Jordan, Lavell, Henrickson, Jens M.
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US10/144,882
• Publication Number:
  US 20030210171A1
• Time in Patent Office: 617 Days
• Field of Search: 342/25, 342/61, 342/62, 342/63, 342/64, 342/65, 342/89, 342/98, 342/102, 342/103, 342/118, 342/127, 342/145-158, 342/175, 342/194, 342/195, 342/196, 342/197, 342/417, 342/422, 342/423-427, 342/442-446, 342/107, 342/120
• US Class Current: 342/127
• CPC Class Codes: G01S 13/18 wherein range gates are used
• CPC Class Codes: G01S 13/20 whereby multiple time-around echoes are used or eliminated
• CPC Class Codes: G01S 13/288 phase modulated
• CPC Class Codes: G01S 13/42 Simultaneous measurement of distance and other co-ordinates indirect measurement G01S13/46
• CPC Class Codes: G01S 13/524 based upon the phase or frequency shift resulting from movement of objects, with reference to the transmitted signals, e.g. coherent MTi
• CPC Class Codes: G01S 13/70 for range tracking only
• CPC Class Codes: G01S 13/882 for altimeters measuring height using barometric means G01C5/06
• CPC Class Codes: G01S 13/935 for terrain-avoidance
• CPC Class Codes: G01S 3/48 the waves arriving at the antennas being continuous or intermittent and the phase difference of signals derived therefrom being measured
• CPC Class Codes: G01S 7/292 Extracting wanted echo-signals

Abstract

A phase processor is disclosed which is configured to receive processed radar return data from a left radar channel, a right radar channel, and an ambiguous radar channel. The phase processor comprises a plurality of phase detectors each with an input and a reference input. The phase detectors are configured to determine a phase difference between radar return data received at the input and radar return data received at the reference input.

Claims

1. A phase processor comprising a plurality of phase detectors, each said phase detector determining a phase difference between any two of left radar channel return data, right radar channel return data, and ambiguous radar channel return data.

2. A phase processor according to claim 1 wherein at least one of said phase detectors is configured to receive ambiguous radar channel return data and receive left radar channel return data, said detector determining a phase difference between the ambiguous radar channel return data and the left radar channel return data.

3. A phase processor according to claim 1 wherein at least one of said phase detectors is configured to receive right radar channel return data and receive ambiguous radar channel return data, said detector determining a phase difference between the right radar channel return data and the ambiguous radar channel return data.

4. A phase processor according to claim 1 wherein at least one of said phase detectors is configured to receive right radar channel return data and receive left radar channel return data, said detector determining a phase difference between the right radar channel return data and the left radar channel return data.

5. A phase processor according to claim 1 wherein said phase detector comprises:

an input;

a reference input;

a first in-phase all pass filter connected to said input;

a first quadrature all pass filter connected to said input;

a second in-phase all pass filter connected to said reference input; and

a second quadrature all pass filter connected to said reference input.

6. A phase processor according to claim 5 further comprising:

a first multiplier configured to multiply outputs from said first in-phase all pass filter and said second quadrature all pass filter;

a second multiplier configured to multiply outputs from said second in-phase all pass filter and said first quadrature all pass filter;

a third multiplier configured to multiply outputs from said first in-phase all pass filter and said second in-phase all pass filter; and

a fourth multiplier configured to multiply outputs from said first quadrature all pass filter and said second quadrature all pass filter.

7. A phase processor according to claim 6 further comprising:

a subtraction element; and

an addition element, said subtraction element configured to subtract an output of said second multiplier from an output of said first multiplier, said addition element configured to add an output of said third multiplier to an output of said fourth multiplier.

8. A phase processor according to claim 7 further comprising a processing element configured to determine an arctangent of an output of said subtraction element divided by an output of said addition element, the arctangent being the phase difference, in radians, between radar return data received at said input and radar return data received at said reference input.

9. A phase processor according to claim 5 wherein said first in-phase all pass filter, said first quadrature all pass filter, said second in-phase all pass filter, and said second quadrature all pass filter each comprise four cascaded second order infinite impulse response (IIR) filters.

10. A phase processor according to claim 9 wherein said second order IIR filters operate according to output=((A0×

input)+(A1×

P_in)+(A2×

PP_in)−

(B1×

P_out)−

(B2×

PP_out))/B0, where P_in is an input from a previous sample, PP_in is an input from two samples previous, P_out is an output from the previous sample, PP_out is an output from two samples previous, and A0, A1, A2, B0, B1, and B2 are coefficients.

11. A phase processor according to claim 10 wherein said first in-phase all pass filter and said second in-phase all pass filter comprise:

a first IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

a/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

a/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

a/T)+w0×

w0, B1=(−

8.0/T)/T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

a/T)+w0×

w0, where a=1.0/0.3225, w0=57.956, and T=1.0/a base band sampling frequency;

a second IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

b/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

b/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

b/T)+w0×

w0, B1=(−

8.0/T)/T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

b/T)+w0×

w0, where b=1.0/0.4071, w0=1198.2, and T=1.0/a base band sampling frequency;

a third IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

c/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

c/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

c/T)+w0×

w0, B1=(−

8.0/T)/T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

c/T)+w0×

w0, where c=1.0/0.4073, w0=16974.0, and T=1.0/a base band sampling frequency; and

a fourth IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

d/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

d/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

d/T)+w0×

w0, B1=(−

8.0/T)/T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

d/T)+w0×

w0, where d=1.0/0.3908, w0=259583.5, and T=1.0/a base band sampling frequency.

12. A phase processor according to claim 10 wherein said first quadrature all pass filter and said second quadrature all pass filter comprise:

a first IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

e/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

e/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

e/T)+w0×

w0, B1=(−

8.0/T)T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

e/T)+w0×

w0, where e=1.0/0.3908, w0=152.05, and T=1.0/a base band sampling frequency;

a second IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

f/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

f/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

f/T)+w0×

w0, B1=(−

8.0/T)/T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

f/T)+w0×

w0, where f=1.0/0.4073, w0=2326.03, and T=1.0/a base band sampling frequency;

a third IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

g/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

g/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

g/T)+w0×

w0, B1=(−

8.0/T)/T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

g/T)+w0×

w0, where g=1.0/0.4071, w0=32949.65, and T=1.0/a base band sampling frequency; and

a fourth IIR filter configured with coefficients A2=(4.0/T)/T+(2.0×

w0×

h/T)+w0×

w0, A1=(−

8.0/T)/T+2.0×

w0×

w0, A0=(4.0/T)/T−

(2.0×

w0×

h/T)+w0×

w0, B2=(4.0/T)/T−

(2.0×

w0×

h/T)+w0×

w0, B1=(−

8.0/T)/T+2.0×

w0×

w0, and B0=(4.0/T)/T+(2.0×

w0×

h/T)+w0×

w0, where h=1.0/0.3225, w0=681178.9, and T=1.0/a base band sampling frequency.

13. A method for processing radar return data, the radar return data including radar return data received at each of a right radar channel, a left radar channel, and an ambiguous radar channel, said method comprising:

receiving the radar return data at a phase processor; and

determining phase differences between the left, right, and ambiguous radar channels.

14. A method according to claim 13 wherein determining phase differences between the left, right, and ambiguous radar channels comprises:

determining a phase difference between the ambiguous radar channel return data and the left radar channel return data;

determining a phase difference between the right radar channel return data and the ambiguous radar channel return data; and

determining a phase difference between the right radar channel return data and the left radar channel return data.

15. A method according to claim 14 wherein receiving the radar return data at a phase processor comprises:

receiving ambiguous radar channel return data at an input of a first phase detector within the phase processor;

receiving left radar channel return data at a reference input of the first phase detector;

receiving right radar channel return data at an input of a second phase detector within the phase processor;

receiving ambiguous radar channel return data at a reference input of the second phase detector;

receiving right radar channel return data at an input of a third phase detector within the phase processor; and

receiving left radar channel return data at a reference input of the third phase detector.

16. A method according to claim 14 wherein the phase processor includes a plurality of phase detectors, the phase detectors having an input connected to a first in-phase all pass filter and to a first quadrature all pass filter, and a reference input connected to a second in-phase all pass filter and to a second quadrature all pass filter, wherein determining a phase difference comprises:

multiplying outputs from the first in-phase all pass filter and the second quadrature all pass filter with a first multiplier;

multiplying outputs from the second in-phase all pass filter and the first quadrature all pass filter with a second multiplier;

multiplying outputs from the first in-phase all pass filter and the second in-phase all pass filter with a third multiplier;

multiplying outputs from the first quadrature all pass filter and the second quadrature all pass filter with a fourth multiplier;

subtracting an output of the second multiplier from an output of the first multiplier;

adding an output of the third multiplier to an output of the fourth multiplier; and

determining an arctangent of the subtraction result divided by the addition result, the arctangent being the phase difference, in radians, between radar return data received at the input and radar return data received at the reference input.

17. A, method according to claim 16 wherein the in-phase all pass filters and the quadrature all pass filters comprise four cascaded second order infinite impulse response (IIR) filters.

18. A radar signal processing circuit comprising:

a radar gate correlation circuit that samples radar return data from left, right, and ambiguous radar channels at a sampling rate;

a correlation bass pass filter that processes the sampled radar return data to form a continuous wave (CW) signal;

a mixer that down samples an in-phase component and a quadrature component of the CW signal to a doppler frequency;

a band pass filter receiving the doppler frequency and centered on the doppler frequency; and

a phase processor that receives filtered radar return data from said band pass filter, said phase processor comprising a plurality of phase detectors, each said phase detector determining a phase difference between a respective two of the left radar channel return data, the right radar channel return data, and the ambiguous radar channel return data.

19. A radar signal processing circuit according to claim 18 wherein:

a first of said phase detectors receives ambiguous radar channel return data and left radar channel return data, said detector determining a phase difference between the ambiguous radar channel return data and the left radar channel return data;

a second of said phase detectors receives right radar channel return data and ambiguous radar channel return data, said detector determining a phase difference between the right radar channel return data and the ambiguous radar channel return data; and

a third of said phase detectors receives right radar channel return data and left radar channel return data, said detector determining a phase difference between the right radar channel return data and the left radar channel return data.

20. A radar signal processing circuit according to claim 18 wherein said phase detectors each comprise:

an input;

a reference input;

a first in-phase all pass filter connected to said input;

a first quadrature all pass filter connected to said input;

a second in-phase all pass filter connected to said reference input; and

a second quadrature all pass filter connected to said reference input.

21. A radar signal processing circuit according to claim 20 wherein said phase detectors comprise:

a first multiplier configured to multiply outputs from said first in-phase all pass filter and said second quadrature all pass filter;

a second multiplier configured to multiply outputs from said second in-phase all pass filter and said first quadrature all pass filter;

a third multiplier configured to multiply outputs from said first in-phase all pass filter and said second in-phase all pass filter; and

a fourth multiplier configured to multiply outputs from said first quadrature all pass filter and said second quadrature all pass filter;

a subtraction element configured to subtract an output of said second multiplier from an output of said first multiplier;

an addition element configured to add an output of said third multiplier to an output of said fourth multiplier, and

a processing element configured to determine an arctangent of an output of said subtraction element divided by an output of said addition element, the arctangent being the phase difference, in radians, between radar return data received at said input and radar return data received at said reference input.

22. A radar signal processing circuit according to claim 20 wherein said all pass filters comprise four cascaded second order infinite impulse response (IIR) filters.