Z test and conditional merger of colliding pixels during batch building

• US 6,680,737 B2
• Filed: 12/12/2002
• Issued: 01/20/2004
• Est. Priority Date: 07/31/1999
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Alcorn, Byron A, Emmot, Darel N, Ashburn, Jon L
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US10/317,526
• Publication Number:
  US 20030090486A1
• Time in Patent Office: 404 Days
• Field of Search: 345/503, 345/506, 345/522, 345/531, 345/533, 345/545, 345/570, 345/422, 345/421, 710/39, 710/52, 710/54, 710/310
• US Class Current: 345/531
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/405 using Z-buffer
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel'"'"'s BEN. The buffered BEN may be replaced with the logical OR of the stored BEN and the incoming pixel'"'"'s BEN.

Claims

1. A method for conserving frame buffer memory bandwidth in a computer graphics system, comprising the steps of:

receiving pixel commands from a pipeline;

detecting a pixel collision between an incoming pixel command and a buffered pixel command stored in the batch-building buffer;

performing a depth comparison between the incoming pixel command and the buffered pixel command; and

storing representations of each received pixel command in a batch-building buffer only when the received pixel command passes the depth comparison, thereby accumulating a batch of frame buffer memory accesses.

2. A method according to claim 1, further comprising:

when the incoming pixel command passes the depth comparison, determining, based on the current rendering mode of the pipeline, whether the incoming pixel command may be merged with the buffered pixel command; and

when it is determined that the incoming pixel command may be merged with the buffered pixel command, merging the incoming pixel command with the buffered pixel command.

3. A method according to claim 2, further comprising:

when it is determined that the incoming pixel command may not be merged with the buffered pixel command, flushing a portion of the buffer contents containing the buffered pixel command.

4. A method according to claim 2, wherein determining whether the incoming pixel command may be merged with the buffered pixel command comprises testing whether the current rendering mode of the pipeline includes read-modify-write mode.

5. A method according to claim 2, wherein merging the incoming pixel command with the buffered pixel command comprises:

overwriting the RGBA components of the buffered pixel command with those of the incoming pixel command, but only those components that correspond to asserted BEN bits in the incoming pixel command; and

leaving intact those components that correspond to unasserted BEN bits in the incoming pixel command.

6. A method according to claim 2:

wherein storing a representation of the incoming pixel commands in the batch-building buffer comprises storing the BEN bits of received pixel commands; and

wherein merging the incoming pixel command with the buffered pixel command comprises;

determining the logical OR of the buffered BEN bits and the incoming BEN bits; and

storing the results of the logical OR determination in place of the buffered BEN bits.

7. Circuitry for conserving frame buffer memory bandwidth in a computer graphics system, comprising:

a bus for receiving pixel commands from a pipeline;

a buffer for storing representations of the received pixel commands to accumulate a batch of frame buffer memory accesses;

collision detect circuitry for detecting a pixel collision between an incoming pixel command and a buffered pixel command; and

z compare circuitry for performing a depth comparison between the incoming pixel command and the buffered pixel command,

wherein the representation of each received pixel command is stored in the batch-building buffer only when the received pixel command passes the depth comparison.

8. Circuitry according to claim 7, wherein:

the location of the buffer at which the representations of the received pixel commands are stored is determined at least in part responsive to the addresses specified by the received pixel commands;

each location of the buffer containing a stored representation of a pixel command has a unique valid bit associated with it; and

the collision detect circuitry comprises circuitry for mapping the incoming pixel command to a target buffer location and testing the valid bit associated with the target buffer location.

9. Circuitry according to claim 7, comprising:

merge and switch circuitry for conditionally merging a portion of the incoming pixel command with a portion of the buffered pixel command.

10. Circuitry according to claim 9, wherein:

the buffer includes space for the RGBA components of each stored pixel representation of a pixel command; and

the merge and switch circuitry comprises circuitry for overwriting the RGBA components of the buffered pixel command with those of the incoming pixel command, but only those components that correspond to asserted BEN bits in the incoming pixel command.

11. Circuitry according to claim 9, wherein:

the buffer includes space for the BEN bits of each stored pixel representation of a pixel command; and

the merge and switch circuitry comprises circuitry for determining the logical OR of the buffered BEN bits and the incoming BEN bits, and storing the results of the logical OR determination in place of the buffered BEN bits.