Logic process DRAM

• US 6,680,859 B1
• Filed: 01/02/2003
• Issued: 01/20/2004
• Est. Priority Date: 06/28/2000
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Lee, Winston, Lee, Peter, Sutardja, Sehat
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/336,423
• Time in Patent Office: 383 Days
• Field of Search: 365/185.01, 365/185.02, 365/185.05, 365/63, 438/253, 438/254
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

Claims

1. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit including a substrate and a plurality of memory cells, each memory cell comprising:

a transistor, including a gate, the gate comprising polysilicon;

a gate oxide arranged between the gate and the substrate;

a cell plate, the cell plate comprising one of polysilicon and a metal conductor, and the cell plate being physically isolated from the gate by a minimum displacement; and

a dielectric material arranged between the cell plate from the substrate, the dielectric material having a high dielectric constant,

wherein a direction of the minimum displacement is substantially orthogonal to the substrate such that a component of the minimum displacement parallel to the substrate is substantially zero.

2. The device of claim 1, the dielectric material comprising tantalum oxide.

3. The device of claim 1, the dielectric material comprising aluminum oxide.

4. The device of claim 1, the dielectric material comprising oxinitride.

5. The device of claim 1, the DRAM unit being manufactured using a logic process.

6. The device of claim 1, the DRAM unit being manufactured using a DRAM process.

7. A semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, the DRAM unit including a substrate and a plurality of memory cells, each memory cell comprising:

a transistor, including a gate, the gate comprising polysilicon;

a gate oxide arranged between the gate and the substrate;

a cell plate, the cell plate comprising one of polysilicon and a metal conductor, and the cell plate being physically isolated from the gate; and

a dielectric material arranged between the cell plate and the substrate, the dielectric material having a high dielectric constant,

wherein the cell plate and the gate are physically located on different vertical levels as seen from the substrate.

8. The device of claim 7, the dielectric material comprising tantalum oxide.

9. The device of claim 7, the dielectric material comprising aluminum oxide.

10. The device of claim 7, the dielectric material comprising oxinitride.

11. The device of claim 7, the DRAM unit being manufactured using a logic process.

12. The device of claim 7, the DRAM unit being manufactured using a DRAM process.

13. An apparatus for reducing area in a DRAM device, the DRAM device including a substrate means and a plurality of means for storing data, each means for storing data comprising:

a transistor means for switching, including a gate means, the gate means comprising polysilicon;

gate insulating means for insulating the gate means from the substrate means;

a cell plate means for providing an electric field, the cell plate means comprising one of polysilicon and a metal conductor, and the cell plate means being physically isolated from the gate means by a minimum displacement to prevent short circuits; and

a dielectric means for separating the cell plate means from the substrate means, the dielectric means having a high dielectric constant,

wherein a direction of the minimum displacement is substantially orthogonal to the substrate means, such that a component of the minimum displacement parallel to the substrate means is substantially zero.

14. The apparatus of claim 13, the dielectric means comprising tantalum oxide.

15. The apparatus of claim 13, the dielectric means comprising aluminum oxide.

16. The apparatus of claim 13, the dielectric means comprising oxinitride.

17. The apparatus of claim 13, the DRAM device being manufactured using a logic process.

18. The apparatus of claim 13, the DRAM device being manufactured using a DRAM process.

19. An apparatus for reducing area in a DRAM device, the DRAM device including a substrate means and a plurality of means for storing data, each means for storing data comprising:

a transistor means for switching, including a gate means, the gate means comprising polysilicon;

gate insulating means for insulating the gate means from the substrate means;

a cell plate means for providing an electric field, the cell plate means comprising one of polysilicon and a metal conductor, and the gate means being physically located on a first vertical level as seen from the substrate means and the cell plate means being physically located on a second vertical level as seen from the substrate means; and

a dielectric means for separating the cell plate means from the substrate means, the dielectric means having a high dielectric constant.

20. The apparatus of claim 19, the dielectric means comprising tantalum oxide.

21. The apparatus of claim 19, the dielectric means comprising aluminum oxide.

22. The apparatus of claim 19, the dielectric means comprising oxinitride.

23. The apparatus of claim 19, the DRAM device being manufactured using a logic process.

24. The apparatus of claim 19, the DRAM device being manufactured using a DRAM process.

25. A method of reducing area in a DRAM device, the DRAM device including a substrate and a plurality of memory cells, each memory cell including a transistor having a gate comprising polysilicon and a cell plate, the method comprising the steps of:

arranging a gate oxide between the gate and the substrate;

physically isolating the cell plate from the gate by a minimum displacement to prevent short circuits; and

arranging a dielectric material having a high dielectric constant between the cell plate and the substrate,

wherein a direction of the minimum displacement is substantially orthogonal to the substrate, such that a component of the minimum displacement parallel to the substrate is substantially zero.

26. The method of claim 25, the dielectric material comprising tantalum oxide.

27. The method of claim 25, the dielectric material comprising aluminum oxide.

28. The method of claim 25, the dielectric material comprising oxinitride.

29. The method of claim 25, the DRAM device being manufactured using a logic process.

30. The method of claim 25, the DRAM device being manufactured using a DRAM process.

31. A method of reducing area in a DRAM device, the DRAM device including a substrate and a plurality of memory cells, each memory cell including a transistor having a gate comprising polysilicon and a cell plate, the method comprising the steps of:

arranging a gate oxide between the gate and the substrate;

locating the gate on a first vertical level as seen from the substrate;

locating the cell plate on a second vertical level as seen from the substrate; and

arranging a dielectric material having a high dielectric constant between the cell plate and the substrate.

32. The method of claim 31, the dielectric material comprising tantalum oxide.

33. The method of claim 31, the dielectric material comprising aluminum oxide.

34. The method of claim 31, the dielectric material comprising oxinitride.

35. The method of claim 31, the DRAM device being manufactured using a logic process.

36. The method of claim 31, the DRAM device being manufactured using a DRAM process.