Semiconductor device

• US 6,680,869 B2
• Filed: 04/12/2002
• Issued: 01/20/2004
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Tadokoro, Haruko, Sakata, Takeshi, Nagashima, Osamu, Nakagome, Yoshinobu, Sonoda, Takahiro, Morita, Sadayuki
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/120,447
• Publication Number:
  US 20020118575A1
• Time in Patent Office: 648 Days
• Field of Search: 365/189.05, 365/191, 365/193, 365/233
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

Claims

1. A semiconductor device, comprising:

a plurality of memory cells; and

a control circuit which controls the timing to write data into one of the said memory cells;

wherein a clock signal and a data strobe signal are fed into said control circuit to control said timing,

wherein said control circuit comprises a sequential logic circuit, and

wherein said clock signal and said data strobe signal are fed into said sequential logic circuit and the output of the sequential logic circuit is fed into a logic circuit which receives said write data.

2. The semiconductor device according to claim 1,

wherein said sequential logic circuit is a set/reset flip-flop circuit, and

wherein said memory cells are DRAM cells.