Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interrupt

• US 6,681,280 B1
• Filed: 10/04/2000
• Issued: 01/20/2004
• Est. Priority Date: 10/29/1999
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Miyake, Hideo, Nakamura, Yasuki, Suga, Atsuhiro
• Primary Examiner(s): Lefkowitz, Sumati
• Application Number:
  US09/678,732
• Time in Patent Office: 1,203 Days
• Field of Search: 710/260-269, 710/46-50, 712/227, 712/228, 712/244, 714/32-36
• US Class Current: 710/261
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

Claims

1. An interrupt control apparatus having a function of normal interrupt and a function of break-interrupt, said apparatus comprising:

a first information holding section for holding, at the time of a normal interrupt, operation information of a processor before said normal interrupt;

a second information holding section for holding, at the time of a break-interrupt, operation information of said processor before said break-interrupt;

a return operation specifying section for specifying whether a return operation from a normal interrupt state or a return operation from a break-interrupt state is to be performed in returning from an interrupt operation; and

an interrupt return section for re-setting operation information held in said first information holding section or operation information held in said second information holding section in accordance with operation contents specified by said return operation specifying section, and thereby returning the state of said processor from an interrupt operation state to a state before the interrupt.

2. An apparatus according to claim 1, wherein said second information holding section holds an instruction address before the break-interrupt, to which said processor is to return from the break-interrupt operation state.

3. An apparatus according to claim 2, wherein said second information holding section further holds the processor state before the break-interrupt.

4. An apparatus according to claim 2, wherein said second information holding section further holds a factor of the break-interrupt.

5. An apparatus according to claim 2, wherein said second information holding section further holds the processor state before the break-interrupt and a factor of the break-interrupt.

6. An apparatus according to claim 1, wherein said return operation specifying section specifies the return operation using flag information which is set at the time of interrupt and shows whether the interrupt is the break-interrupt or not.

7. An apparatus according to claim 1, wherein said return operation specifying section specifies the return operation in accordance with a value described in an operand of an interrupt return instruction.

8. An apparatus according to claim 1, wherein said return operation specifying section specifies the return operation in accordance with contents of an instruction field of an interrupt return instruction.

9. An interrupt control method comprising the steps of:

when a normal interrupt occurs, holding operation information of a processor before said normal interrupt in a first information holding section;

when a break-interrupt occurs, holding operation information of said processor before said break-interrupt in a second information holding section different from said first information holding section, and setting a flag for showing whether or not the break-interrupt state is set, to the break-interrupt state; and

in returning said processor from the interrupt state to a state before the interrupt, selecting and restoring one of operation information in said first information holding section and operation information in said second information holding section in accordance with a value of said flag.

10. An interrupt control method comprising the steps of:

when a normal interrupt occurs, holding operation information of a processor before said normal interrupt in a first information holding section;

when a break-interrupt occurs, holding operation information of said processor before said break-interrupt in a second information holding section different from said first information holding section; and

in returning said processor from the interrupt state to a state before the interrupt, selecting and restoring one of operation information in said first information holding section and operation information in said second information holding section in accordance with contents of an interrupt return instruction.

11. An interrupt control method for an interrupt control apparatus having a function of normal interrupt and a function of break-interrupt, said method comprising the steps of:

when a break-interrupt occurs, holding at least an instruction address before said break-interrupt, to which a processor is to return from a break-interrupt state, and setting a flag for representing whether or not said break-interrupt state is set, to said break-interrupt state; and

in returning said processor from said break-interrupt state to a state before said break-interrupt, canceling said flag for representing said break-interrupt state, and restoring said instruction address which has been held.

12. A method according to claim 11, further comprising the steps of:

when said break-interrupt occurs, holding not only said instruction address but also the processor state before said break-interrupt, and in returning said processor from said break-interrupt state to said state before said break-interrupt, restoring said processor state, which has been held.

13. A method according to claim 11, further comprising the step of:

when said break-interrupt occurs, holding not only said instruction address but also a factor of said break-interrupt.