Coherent data apparatus for an on-chip split transaction system bus

• US 6,681,283 B1
• Filed: 08/12/1999
• Issued: 01/20/2004
• Est. Priority Date: 08/12/1999
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Thekkath, Radhika, Uhler, G. Michael
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/373,094
• Time in Patent Office: 1,622 Days
• Field of Search: 710/305, 710/110, 710/107, 710/113, 710/240, 710/36, 711/100, 711/113, 711/141, 711/146, 709/200, 709/209, 370/462
• US Class Current: 710/305
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A cache coherency system for an on-chip computing bus is provided. The coherency system contains a coherency credit counter within each master device on the on-chip bus for monitoring the resources available on the bus for coherent transactions, a coherency input buffer for storing coherent transactions, and a cache for storing coherent data. The coherency credit counter tracks coherent transactions pending in a memory controller, and delays coherent transactions from being placed on the bus if coherent resources are not available in the memory controller. When resources become available in the memory controller, the memory controller signals the coherency system in each of the master devices. The coherency system is coupled to a split transaction tracking and control to establish transaction ID'"'"'s for each coherent transaction initiated by its master device, and presents a transaction ID along with an address portion of each coherent transaction.

Claims

1. An on-chip system bus having a plurality of data master devices that perform data transfers with memory, each of the master devices comprising:

a bus interface, for allowing its master device to communicate with the on-chip system bus; and

a cache coherency system having a cache, coupled to said bus interface, for maintaining coherency between said cache and the memory, wherein said cache coherency system comprises a coherency credit counter, for counting pending coherent operations on the system bus.

2. The on-chip system bus, as recited in claim 1 wherein the on-chip system bus is a split-transaction bus.

3. The on-chip system bus, as recited in claim 1 wherein a data master device is a device capable of initiating a data transfer on the system bus.

4. The on-chip system bus, as recited in claim 1 wherein a bus arbiter is configured to arbitrate between the plurality of data master devices for access to the system bus.

5. The on-chip system bus, as recited in claim 1 wherein the data transfers are in response to a read command occurring on the system bus.

6. The on-chip system bus, as recited in claim 1 wherein said bus interface comprises an address portion and a data portion.

7. The on-chip system bus, as recited in claim 1 wherein said cache coherency system insures that two or more of the plurality of data master devices can have the same data in a consistent state in their caches.

8. The on-chip system bus, as recited in claim 1 wherein if one of the plurality of data master devices modifies datum in its cache, said cache coherency system within another one of the plurality of data master devices invalidates said datum in its cache.

9. The on-chip system bus, as recited in claim 1 wherein if one of the plurality of data master devices modifies datum in its cache, the one of the plurality of data master devices changes a state of said datum in its cache to dirty.

10. The on-chip system bus, as recited in claim 9 wherein if another one of the plurality of data master devices attempts to read said datum, the one of the plurality of data master devices writes back said dirty datum to the memory prior to the other one of the plurality of data master devices reading said datum.

11. The on-chip system bus, as recited in claim 10 wherein the one of the plurality of data master devices changes the state of said datum in its cache to shared.

12. The on-chip system bus, as recited in claim 1 wherein if one of the plurality of master devices contains datum in its cache, and said datum has a state of exclusive, and another one of the plurality of master devices attempts to read said datum from the memory, the one of the plurality of master devices changes the state of said datum in its cache to shared.

13. The on-chip system bus, as recited in claim 1 wherein if one of the plurality of master devices contains datum in its cache, and said datum has a state of clean or dirty, and another one of the plurality of master devices initiates a read exclusive probe associated with said datum, the one of the plurality of master devices changes the state of said datum in its cache to invalid.

14. The on-chip system bus, as recited in claim 13 wherein if said state of said datum in the one of the plurality of master devices is dirty, upon recognizing said read exclusive probe, the one of the plurality of master devices causes said dirty datum to be written back to the memory.

15. The on-chip system bus, as recited in claim 1 wherein if one of the plurality of master devices contains datum in its cache, and said datum has a state of clean or dirty, and another one of the plurality of master devices initiates an upgrade-probe associated with said datum, the one of the plurality of master devices changes the state of said datum in its cache to invalid.

16. The on-chip system bus, as recited in claim 1 wherein if one of the plurality of master devices contains datum in its cache, and said datum has a state of clean or dirty, and another one of the plurality of master devices initiates a write-exclusive associated with said datum, the one of the plurality of master devices changes the state of said datum in its cache to invalid.

17. The on-chip system bus, as recited in claim 16, wherein if said datum in the one of the plurality of master devices is dirty, the one of the plurality of master devices writes back said datum to the memory.

18. The on-chip system bus, as recited in claim 1 wherein said cache coherency system insures that the plurality of data master devices do not use invalid data values.

19. The on-chip system bus, as recited in claim 1 wherein said coherency credit counter is coupled to a memory controller having coherency buffer management, said coherency credit counter monitoring available buffer space in said coherency buffer management.

20. The on-chip system bus, as recited in claim 19 wherein if said coherency credit counter determines that there is no available buffer space in said coherency buffer management, said cache coherency system causes its master device to delay coherent transactions until said coherency credit counter determines that there is available buffer space in said coherency buffer management.

21. The on-chip system bus, as recited in claim 1 wherein said cache coherency system further comprises:

a coherency input buffer, coupled to said coherency credit counter, said coherency input buffer designated to hold coherent transactions.

22. The on-chip system bus, as recited in claim 21 wherein the size of said coherency input buffer is the same for all of the plurality of data master devices.

23. The on-chip system bus, as recited in claim 1 further comprising:

a memory controller, coupled to the system bus, said memory controller having coherency buffer management, said coherency buffer management managing all coherent transactions initiated by the plurality of data master devices.

24. The on-chip system bus, as recited in claim 23 wherein said coherency buffer management, upon recognition of a coherent transaction initiated by one of the plurality of data master devices, delays servicing of said coherent transaction by said memory controller until it receives coherency state information from the other of the plurality of data master devices.

25. The on-chip system bus, as recited in claim 24 wherein said coherency buffer management, upon receiving said coherency state information from the other of the plurality of data master devices, alerts said memory controller to retrieve datum associated with said coherent transaction.

26. The on-chip system bus, as recited in claim 24 wherein said coherency state information comprises:

dirty, clean, invalid, or don'"'"'t-know-yet states.

27. A processing device configured to access an on-chip bus to perform a coherent data transfer, the processing device comprising:

a bus interface, for coupling the processing device to the on-chip bus; and

a cache coherency system having a cache, coupled to said bus interface, for determining whether the coherent data transfer can begin on the on-chip bus;

wherein the coherent data transfer cannot begin on the on-chip bus if coherent transaction buffer space external to the processing device is unavailable.

28. The processing device, as recited in claim 27 wherein said coherent transaction buffer space is located within a memory controller that is coupled to the on-chip bus.

29. The processing device, as recited in claim 27 wherein said cache coherency system comprises a coherency credit counter for monitoring the availability of said coherent transaction buffer space.

30. A processing device configured to access an on-chip bus to perform a coherent data transfer, the processing device comprising:

a bus interface, for coupling the processing device to the on-chip bus;

a cache coherency system having a cache, coupled to said bus interface, for determining whether the coherent data transfer can begin on the on-chip bus; and

split transaction tracking and control, coupled to said bus interface, for establishing a transaction ID for the coherent data transfer, wherein said transfer has split address and data portions.

31. The processing device as recited in claim 30 wherein said split transaction tracking and control comprises:

a transaction buffer, for temporarily storing said transaction ID so that it may be presented along with said coherent data transfer on the on-chip bus.

32. The processing device as recited in claim 30 wherein said transaction ID comprises:

a device ID, for identifying a device that initiates said coherent data transfer; and

a transaction tag, for identifying said coherent data transfer.

33. A multi-master split-transaction on-chip system bus for interfacing a plurality of master devices to a main memory, wherein each of the plurality of master devices have a bus interface, each of the plurality of master devices comprising:

a cache coherency system, having a cache, coupled to the bus interface, for temporarily storing data retrieved from the main memory, for insuring that its master device does not operate on invalid data, and for monitoring a plurality of coherent data transactions; and

split transaction tracking and control, coupled to the bus interface, for establishing transaction ID'"'"'s for each of the plurality of coherent data transactions, wherein said transactions have split address and data portions.

34. The multi-master split-transaction on-chip system bus as recited in claim 33 wherein said cache coherency system comprises:

a coherency credit counter, for tracking the number of pending coherent data transactions; and

a coherency input buffer, coupled to said cache, said coherency input buffer designated to hold the plurality of coherent data transactions.

35. The multi-master split-transaction on-chip system bus as recited in claim 33 wherein said split transaction tracking and control comprises:

means for generating a transaction tag that may be presented along with said address portion of the plurality of coherent data transactions.

36. A computer program product for use with a computing device, the computer program product comprising:

a computer usable medium having computer readable program code embodied in said medium for causing an on-chip computing bus to be described, said computer readable program code comprising;

first computer readable program code for providing a cache coherency system within a master device, to maintain data coherency between a cache and a main memory for coherent data transactions; and

second computer readable program code for providing split transaction tracking and control to establish transaction ID'"'"'s for said coherent data transactions to be presented on the on-chip computing bus, wherein said transactions have split address and data portions.

37. A method for performing a coherent data transfer on an on-chip bus, comprising:

providing a processing device to access the on-chip bus;

monitoring availability of a coherent transaction buffer space external to the processing device; and

determining whether the coherent data transfer can begin on the on-chip bus based on the availability of the coherent transaction buffer space.

38. The method as recited in claim 37 further comprising:

delaying the coherent data transfer if said step of determining determines that the coherent transaction buffer space is unavailable.

39. The method as recited in claim 37 further comprising:

beginning the coherent data transfer if said step of determining determines that the coherent transaction buffer space is available.