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Coherent data apparatus for an on-chip split transaction system bus

  • US 6,681,283 B1
  • Filed: 08/12/1999
  • Issued: 01/20/2004
  • Est. Priority Date: 08/12/1999
  • Status: Expired due to Term
First Claim
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1. An on-chip system bus having a plurality of data master devices that perform data transfers with memory, each of the master devices comprising:

  • a bus interface, for allowing its master device to communicate with the on-chip system bus; and

    a cache coherency system having a cache, coupled to said bus interface, for maintaining coherency between said cache and the memory, wherein said cache coherency system comprises a coherency credit counter, for counting pending coherent operations on the system bus.

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