Stress controlled dielectric integrated circuit fabrication
First Claim
1. A method of making an integrated circuit comprising:
- forming on a semiconductor substrate circuitry including multiple integrated circuits having active devices; and
forming a stress-controlled dielectric membrane adjacent said circuitry;
wherein the integrated circuit is able to have a major portion of the semiconductor substrate removed throughout a full extent thereof while retaining its structural integrity.
2 Assignments
0 Petitions
Accused Products
Abstract
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
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Citations
70 Claims
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1. A method of making an integrated circuit comprising:
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forming on a semiconductor substrate circuitry including multiple integrated circuits having active devices; and
forming a stress-controlled dielectric membrane adjacent said circuitry;
wherein the integrated circuit is able to have a major portion of the semiconductor substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of making an integrated circuit comprising:
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forming on a semiconductor substrate circuitry including multiple integrated circuits having active devices; and
forming a stress-controlled dielectric layer adjacent said circuitry;
wherein the integrated circuit is able to have a major portion of the semiconductor substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method of making an integrated circuit comprising:
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forming on a semiconductor substrate circuit including multiple integrated circuits having active devices; and
forming a stress-controlled dielectric layer adjacent said circuitry;
removing a major portion of the semiconductor substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A method of making an integrated circuit comprising:
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forming on a substrate circuitry including multiple integrated circuits having active devices; and
forming a stress-controlled dielectric membrane adjacent said circuitry;
wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (38, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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39. The method of clam 37, wherein said substrate is a semiconductor wafer.
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51. A method of making an integrated circuit comprising:
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forming on a substrate circuitry including multiple integrated circuits having active devices; and
forming a stress-controlled dielectric layer adjacent said circuitry;
wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
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62. A method of making an integrated circuit comprising:
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forming on a substrate circuitry including multiple integrated circuits having active devices; and
forming a stress-controlled dielectric layer adjacent said circuitry;
removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit. - View Dependent Claims (63, 64, 65, 66, 67, 68, 69, 70)
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Specification