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Stress controlled dielectric integrated circuit fabrication

  • US 6,682,981 B2
  • Filed: 02/05/2001
  • Issued: 01/27/2004
  • Est. Priority Date: 04/08/1992
  • Status: Expired due to Term
First Claim
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1. A method of making an integrated circuit comprising:

  • forming on a semiconductor substrate circuitry including multiple integrated circuits having active devices; and

    forming a stress-controlled dielectric membrane adjacent said circuitry;

    wherein the integrated circuit is able to have a major portion of the semiconductor substrate removed throughout a full extent thereof while retaining its structural integrity.

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