Method to create a copper diffusion deterrent interface

• US 6,683,002 B1
• Filed: 08/10/2000
• Issued: 01/27/2004
• Est. Priority Date: 08/10/2000
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Zhou, Mei Sheng, Xu, Yi, Aliyu, Yakub, Sudijono, John Leonard, Gupta, Subhash, Chooi, Simon, Roy, Sudipto Ranendra, Ho, Paul Kwok Keung
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): VU, HUNG K
• Application Number:
  US09/636,580
• Time in Patent Office: 1,265 Days
• Field of Search: 438/618, 438/622, 438/624, 438/634, 438/637, 438/639, 438/666, 438/672, 438/687, 257/758, 257/762, 257/767, 257/773, 257/774
• US Class Current: 438/687
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02263 deposition from the gas or vapour phase
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/314 Inorganic layers H01L21/3105, H01L21/32 take precedence
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76844 Bottomless liners

Abstract

Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Claims

1. A method for forming an interconnect opening comprising:

providing a semiconductor structure having a first dielectric layer and a lower interconnect;

forming a passivation layer over said first dielectric layer and said interconnect;

forming a stack dielectric layer over said passivation layer;

patterning and etching said stack dielectric layer to form an upper interconnect opening;

forming an interface layer of either a copper (I) compound or a copper (II) compound over the passivation layer, on side sidewalls said upper interconnect opening and on top of said stack dielectric layer;

said interface layer is formed by a reaction comprising;

reacting complex with a sulfide-containing compound,

removing said interface layer from the stack dielectric but not from the sidewalls of said upper interconnect opening;

etching the passivation layer and interface layer to open the bottom of the upper interconnect opening.

2. The method of claim 1, wherein said stack dielectric layer consists of one dielectric layer.

3. The method of claim 1, wherein said stack dielectric layer is comprised of a second dielectric layer and a third dielectric layer.

4. The method of claim 3, wherein an etch stop layer is formed between the second and third dielectric layers.

5. The method of claim 1, wherein the method is for forming a dual damascene opening.

6. The method of claim 1, wherein a metal is deposited in the upper interconnect opening to form an upper interconnect.

7. The method of claim 1, wherein a cap layer is formed on the stack dielectric layers.

8.The method of claim 1, wherein the interface layer is a copper sulfide interface layer.

9. The method of claim 1, wherein the interface layer is deposited by using a chemical vapor deposition.

10. The method of claim 1 wherein L in the complex comprises one of the following:

an alkene, an alkyne or a phosphine.

11. The method of claim 1 wherein the sulfide-containing compound comprises either ammonium sulfide or hydrogen sulfide.

12. The method of claim 1, wherein the interface layer is removed partially by plasma-assisted dry etching wherein etching chemistry comprises one or more gases from a group containing hydrogen bromide, chlorine, ammonia, silicon tetrachloride, chlorine-substituted silane, nitrogen, argon and hydrogen.

13. The method of claim 1, wherein the lower interconnect is comprised of one or more conductors from a group containing copper, aluminum, aluminum alloy, tungsten, titanium, titanium nitride, tantalum, tantalum nitride and tungsten nitride.

14. The method of claim 1, wherein the lower interconnect is comprised of copper.

15. The method of claim 1, wherein the dielectric layers are one of the following:

a. non-porous undoped silicon oxide,

b. porous undoped silicon oxide

c. non-porous doped silicon oxide,

d. porous doped silicon oxide,

e. non-porous organic material, porous organic material,

f. non-porous doped organic materials,

g. porous doped organic material,

h. phosphosicate glass, or

i. SiO2.

16. The method of claim 1, wherein the passivation layer is one of the following;

a. silicon nitride,

b. silicon oxynitride,

c. silicon carbide, or

d. boron nitride.

8. The method of claim 8, wherein copper sulfide is be deposited through chemical vapor deposition.

17. A method for forming an interconnect opening comprising:

providing a semiconductor structure having a first dielectric layer and a lower interconnect;

forming a passivation layer over said first dielectric layer and said interconnect;

forming a stack dielectric layer over said passivation layer;

patterning and etching said stack dielectric layer to form an upper interconnect opening;

etching of said passivation layer to open a bottom of the upper interconnect opening;

forming an interface layer of either a copper (I) compound or a copper (II) compound over the lower interconnect, on sidewalls of said upper interconnect opening and on top of said stack dielectric layer;

said interface layer is formed by a reaction comprising;

reacting complex with a sulfide-containing compound.

18. The method of claim 18, wherein said interface layer is removed from the stack dielectric, and from the lower interconnect, but not from the sidewalls of said upper interconnect opening.

19. A method for forming an interconnect opening comprising:

providing a semiconductor structure having a first dielectric layer and a lower interconnect;

forming a passivation layer over said first dielectric layer and said interconnect;

forming a stack dielectric layer over said passivation layer;

patterning and etching said stack dielectric layer to form an upper interconnect opening;

forming an interface layer over the passivation layer, on sidewalls said upper interconnect opening and on top of said stack dielectric layer wherein the interface layer is formed by a reaction comprising;

reacting complex with a sulfide-containing compound;

wherein L in the complex comprises one of the following;

an alkene, an alkyne or a phosphine;

removing said interface layer from the stack dielectric but not from the sidewalls of said upper interconnect opening;

etching the passivation layer and interface layer to open the bottom of the upper interconnect opening.

20. The method of claim 20, wherein copper sulfide is be deposited through chemical vapor deposition.