High voltage semiconductor device having two buffer layer
First Claim
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1. A semiconductor device comprising:
- a first buffer layer of a first conductivity type;
a high resistance layer of the first conductivity type formed on the first buffer layer;
a base layer of a second conductivity type formed on the high resistance layer;
a source region of the first conductivity type in a surface region of the base layer;
a gate electrode insulated from the source region, the base layer and the high resistance layer;
a drain layer of the second conductivity type formed on an opposite side of the first buffer layer from a surface on which the high resistance layer is formed; and
a second buffer layer of the first conductivity type formed between the first buffer layer and the drain layer, an impurity concentration of the second buffer layer being higher than that of the first buffer layer, whereby a thickness of the drain layer is thinner than that of the second buffer layer, and the drain layer is a low impurity injection layer.
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Abstract
In an IGBT, an n buffer layer is formed under an n− high resistance layer in which a MOS gate structure is formed. An n+ buffer layer is formed between the n buffer layer and a p+ drain layer. Since the p+ drain layer is doped at a low dose, the efficiency of carrier injection can be reduced and a high-speed operation is possible without lifetime control. Since no lifetime control is performed, the on-state voltage can be low. Since the n buffer layer does not immediately stop the extension of the depletion layer during a turn-off period, oscillation of the current and voltage is prevented. The n+ buffer layer maintains a sufficient withstand voltage when a reverse bias is applied.
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Citations
10 Claims
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1. A semiconductor device comprising:
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a first buffer layer of a first conductivity type;
a high resistance layer of the first conductivity type formed on the first buffer layer;
a base layer of a second conductivity type formed on the high resistance layer;
a source region of the first conductivity type in a surface region of the base layer;
a gate electrode insulated from the source region, the base layer and the high resistance layer;
a drain layer of the second conductivity type formed on an opposite side of the first buffer layer from a surface on which the high resistance layer is formed; and
a second buffer layer of the first conductivity type formed between the first buffer layer and the drain layer, an impurity concentration of the second buffer layer being higher than that of the first buffer layer, whereby a thickness of the drain layer is thinner than that of the second buffer layer, and the drain layer is a low impurity injection layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsMatsudai, Tomoko, Nakagawa, Akio
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Primary Examiner(s)Baumeister, B. William
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Assistant Examiner(s)Fenty, Jesse A.
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Application NumberUS10/084,051Publication NumberTime in Patent Office698 DaysField of Search257/327-334US Class Current257/328CPC Class CodesH01L 29/66333 Vertical insulated gate bip...H01L 29/66348 with a recessed gateH01L 29/7397 and a gate structure lying ...
