Trench structure for semiconductor devices

• US 6,683,363 B2
• Filed: 07/03/2001
• Issued: 01/27/2004
• Est. Priority Date: 07/03/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Mondt, Johannes P
• Application Number:
  US09/898,133
• Publication Number:
  US 20030006452A1
• Time in Patent Office: 938 Days
• Field of Search: 257/328-332, 257/343, 257/355, 257/487, 257/491, 257/496, 257/499-509
• US Class Current: 257/496
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, comprises a semiconductor substrate, a plurality of parallel trenches formed in the semiconductor substrate, a peripheral trench formed in the semiconductor substrate and spaced from and at least partially surrounding the parallel trenches, a dielectric material lining the trenches, and a conductive material substantially filling the dielectric-lined trenches.

Claims

1. A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, said MOS trench structure comprising:

a semiconductor substrate;

a plurality of non-contiguous parallel trenches formed in the semiconductor substrate, each parallel trench defined by ends, sidewalls and a bottom, and each two adjacent parallel trenches separated by a mesa containing the semiconductor device, said mesas having a mesa width;

a peripheral trench formed in the semiconductor substrate and defined by sidewalls and a bottom, said peripheral trench at least partially surrounding the parallel trenches and having a portion that is spaced from ends of the parallel trenches by a parallel trench to peripheral trench spacing;

a dielectric material lining the parallel and peripheral trenches; and

a conductive material substantially filling the dielectric-lined trenches.

2. The MOS trench structure according to claim 1, wherein the parallel trench to peripheral trench spacing is approximately equal to one half the mesa width.

3. The MOS trench structure according to claim 1, wherein the semiconductor substrate comprises:

a semiconductor contact layer, and

an epitaxially-grown semiconductor layer formed on a first major surface of the semiconductor contact layer, said epitaxially-grown semiconductor layer having a doping concentration that is lower than a doping concentration of the semiconductor contact layer.

4. The MOS trench structure according to claim 3, further comprising:

a first metal contact layer formed on an opposing second major surface of the semiconductor contact layer.

5. The MOS trench structure according to claim 4, wherein the semiconductor device further comprises a second metal layer formed over the mesas and the dielectric-lined, conductive-material-filled parallel and peripheral trenches.

7. The structure according to claim 5, wherein the semiconductor device is a Schottky barrier rectifier and the first and second metal contact layers comprise the cathode and anode contacts for the Schottky barrier rectifier.

12. The structure according to claim 1 wherein the semiconductor device is a rectifier formed in the mesas between adjacent parallel trenches, the rectifier being configured to conduct current vertically in the mesas when biased in the on state.

6. A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, said MOS trench structure comprising:

a semiconductor contact layer;

an epitaxially-grown semiconductor layer formed on a first major surface of the semiconductor contact layer;

a plurality of non-contiguous parallel trenches formed in the epitaxially-grown semiconductor layer, each parallel trench defined by ends, sidewalls and a bottom, and each two adjacent parallel trenches separated by a mesa having a mesa width, said semiconductor device having a gate between each two adjacent parallel trenches, the gates being configured so that a current flows vertically in the semiconductor device when the gates are biased to turn on the semiconductor device; and

a peripheral trench formed in the epitaxially-grown semiconductor layer and defined by sidewalls and a bottom, said peripheral trench at least partially surrounding the parallel trenches and having a portion that is spaced from ends of the parallel trenches by a parallel trench to peripheral trench spacing;

a dielectric material lining the parallel and peripheral trenches; and

a conductive material substantially filling the dielectric-lined trenches.

8. The structure according to claim 6, wherein the parallel trench to peripheral trench spacing is approximately equal to one half the mesa width.

9. A MOS trench structure integrated with a radio frequency field effect transistor (RF FET) for enhancing the breakdown characteristics of the RF FET, said MOS trench structure comprising:

a drain contact layer having a first conductivity type;

an epitaxially-grown semiconductor layer formed on a first major surface of the drain contact layer, said epitaxially-grown semiconductor layer having the same conductivity type as the drain contact layer but with a lower doping concentration;

a first metal contact layer formed on an opposing and second major surface of the drain contact layer;

a plurality of non-contiguous parallel trenches formed in the epitaxially-grown semiconductor layer, each parallel trench defined by ends, sidewalls and a bottom, and adjacent parallel trenches being separated by mesas, which contain the RF FET, the RF FET having gate regions and source regions configured so that a current flows vertically between the source regions and the drain contact layer when the gate regions are biased to turn an the RF FET;

a peripheral trench formed in the epitaxially-grown semiconductor layer and defined by sidewalls and a bottom, said peripheral trench at least partially surrounding the parallel trenches and having a portion that is spaced from ends of the parallel trenches by a parallel trench to peripheral trench spacing;

a dielectric material lining the parallel and peripheral trenches; and

a conductive material substantially filling the dielectric-lined trenches.

10. The structure according to claim 9, wherein the RF FET comprises:

well regions of a second conductivity type formed in upper corners of the mesas, each two well regions in a mesa separated by a gap, wherein the source regions are of the first conductivity type and are formed in the well regions, and the gate regions are formed over portions of the source regions and a portion of the gap with in each mesa.

11. The structure according to claim 9, wherein the parallel trench to peripheral trench spacing is approximately equal to one half a width of the mesas.