Memory expansion module with stacked memory packages and a serial storage unit

• US 6,683,372 B1
• Filed: 11/18/1999
• Issued: 01/27/2004
• Est. Priority Date: 11/18/1999
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Jeffrey, David, Wong, Tayung, Vaidya, Nikhil, Fang, Clement, Mitty, Nagaraj, Robinson, Jay, Carrillo, John
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US09/442,850
• Time in Patent Office: 1,531 Days
• Field of Search: 257/685, 257/686, 257/723, 257/724, 257/777, 257/778, 365/51, 365/52, 365/63, 361/748, 361/760, 361/783
• US Class Current: 257/686
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1024 Identification of the type of error
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H05K 1/181 associated with surface mounted components

Abstract

A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Claims

1. A memory module comprising:

a printed circuit board including a connector edge adapted for insertion within a socket of a computer system, wherein said connector edge includes a plurality of electrical contact pads for conveying electrical signals;

a plurality of stacked memory packages mounted upon said printed circuit board, each of said stacked memory packages including a first memory die and a second memory die, and wherein said first memory die of each of said stacked memory packages forms a portion of a first bank of memory and said second memory die of each of said stacked memory packages forms a portion of a second bank of memory;

a clock driver chip;

a serial storage unit, wherein said serial storage unit stores module identification information and signal line routing information which correlates each of at least some of said contact pads of said connector edge to a corresponding pin of a particular stacked memory package; and

,

at least one line driver chip configured to drive control signals and/or address signals.

2. The memory module as recited in claim 1, wherein said edge connector has 232 of said electrical contact pads.

3. The memory module as recited in claim 1, wherein said connector edge includes contact pads for receiving control signals, said control signals comprising at least one row address strobe (RAS) signal, at least one column address strobe (CAS) signal, at least one write enable (WE) signal, at least one clock enable (CKE) signal, and a least one chip select (CS) signal.

4. The memory module as recited in claim 1, wherein said electrical signals include a plurality of address signals, and wherein said plurality of address signals form an address bus.

5. The memory module as recited in claim 4, wherein said address bus is 14 bits wide.

6. The memory module as recited in claim 1, wherein said electrical signals include a plurality of data signals, and wherein said plurality of data signals form a data path.

7. The memory module as recited in claim 6, wherein said data path is 144 bits wide.

8. The memory module as recited in claim 1, wherein said memory module is configured for use in a system having an error correction subsystem, said error correction subsystem configured to generate a plurality of check words corresponding to a plurality of data blocks.

9. The memory module as recited in claim 1, wherein said serial storage unit is a serial electrically erasable programmable read-only memory (EEPROM).

10. The memory module as recited in claim 1, wherein said first memory die and said second memory die are dynamic random access memory (DRAM) chips.

11. The memory module as recited in claim 1, wherein said memory module is a dual-inline memory module (DIMM).

12. The memory module as recited in claim 1, wherein said memory module has a memory capacity of one gigabyte.

13. The memory module as recited in claim 1, wherein each of said stacked memory packages includes two memory die.

14. A memory module comprising:

a printed circuit board including a plurality of signal lines for conveying electrical signals and a connector edge adapted for insertion within a socket of a computer system, said edge connector having a plurality of contact pads for conveying said electrical signals between said memory module and a memory bus;

a plurality of stacked memory packages, each having two memory die, mounted upon said printed circuit board, each of said stacked memory packages having a plurality of signal pins;

a clock driver chip;

a storage unit for storing module identification and information which correlates said electrical contact pads to said signal pins; and

,

at least one line driver chip for driving electrical signals to said stacked memory packages.

15. The memory module as recited in claim 14, wherein said electrical signals include a plurality of control signals, a plurality of data signals, and a plurality of address signals.

16. The memory module as recited in claim 15, wherein said plurality of data signals form a data path, said data path 144 bits wide.

17. The memory module as recited in claim 15, wherein said plurality of address signals form an address bus, said address bus 14 bits wide.

18. The memory module as recited in claim 15, wherein said control signals include two column address strobe (CAS) signals, two row address strobe (RAS) signals, two write enable (WE) signals, two chip select (CS) signals, and two clock enable (CKE) signals.

19. The memory module as recited in claim 14, wherein said memory module is a Dual Inline Memory Module (DIMM).

20. The memory module as recited in claim 14, wherein said memory die are synchronous dynamic random access memory (SDRAM) chips.

21. The memory module as recited in claim 14 wherein said memory module has 232 of said contact pads.