Integrated circuit with bonding layer over active circuitry

• US 6,683,380 B2
• Filed: 07/10/2002
• Issued: 01/27/2004
• Est. Priority Date: 07/07/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Corsi, Marco, Abbott, Donald C., Efland, Taylor R., Williams, Charles E., Shen, Chi-Cheong, Mai, Quang X., Hutter, Louis N., Buschbom, Milton L., Bucksch, Walter, Erdeljac, John P., Wagensohner, Konrad
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): ANDUJAR, LEONARDO
• Application Number:
  US10/191,453
• Publication Number:
  US 20030036256A1
• Time in Patent Office: 566 Days
• Field of Search: 257/734, 257/764, 257/767, 257/784, 438/613
• US Class Current: 257/734
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48664 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48744 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48764 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/4903 : Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49051 : Connectors having different shapes
• CPC Class Codes: H01L 2224/49111 : the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 : Parallel arrangements
• CPC Class Codes: H01L 2224/49431 : on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/4945 : Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
• CPC Class Codes: H01L 2224/85191 : connecting first both on and outside the semiconductor or solid-state body, i.e. regular and reverse stitches
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Claims

1. An integrated circuit device, comprising:

a silicon substrate;

an active circuit on said substrate, said active circuit having at least one metallization layer thereover;

an electrically conductive bonding surface positioned directly over said active circuit and said metallization layer;

said bonding surface having connector stacks to said metallization layer, each of said stacks being comprised of a stack of the following electrically conductive layers in succession;

an electrically conductive seed metal layer in contact with said metallization layer capable of providing an adhesive and conductive layer for electroplating on its surface, an electroplated support layer secured to said seed metal layer, and at least one wire bonding layer on said support layer; and

at least one wire bonded to said bonding surface directly over said active circuit.

2. The integrated circuit device of claim 1, wherein said seed metal layer is at least in part comprised of titanium.

3. The integrated circuit device of claim 1, wherein said support layer is comprised at least in part of copper.

4. The integrated circuit device of claim 1, wherein said wire bonding layer is comprised at least in part of nickel.

5. The integrated circuit of claim 1, wherein said wire bonding layer is comprised at least in part of palladium.

6. The integrated circuit device of claim 1, wherein said wire bonding layer is comprised of a first layer of a wire bonding substrate material and a second layer of a sacrificial material.

7. The integrated circuit device of claim 1, wherein said wire bonding layer covers at least a portion of the sides of each said stack.

8. The integrated circuit device of claim 1, wherein said integrated circuit further comprises an electrically non-conductive protective layer over said metallization layer and between said stacks.

9. An integrated circuit device, comprising:

a silicon substrate;

an active circuit fabricated on said substrate;

a metallization layer over said active circuit and coupled to said active circuit;

an electrically conductive bonding surface positioned over said active circuit and said metallization layer, said bonding surface having connector stacks to said metallization layer, each of said stacks being comprised of a stack of the following electrically conductive layers in succession;

an electrically conductive seed metal layer in contact with said metallization layer capable of providing an adhesive and conductive layer for electroplating on its surface, an electroplated support layer secured to said seed metal layer, and at least one wire bonding layer on said support layer; and

at least one wire bonded to said bonding surface.

10. The integrated circuit device of claim 9, wherein said bond pads are directly over said stacks.

11. An integrated circuit device, comprising:

a semiconductor substrate;

an active circuit disposed on said substrate;

a metallization layer over said active circuit and coupled to said active circuit;

an electrically conductive bonding surface positioned over said active circuit, said bonding surface having connector stacks to said metallization layer, each of said stacks being comprised of a stack of the following electrically conductive layers in succession;

an electrically conductive seed metal layer capable of providing an adhesive and conductive layer for electroplating on its surface in contact with said metallization layer, an electroplated support layer secured to said seed metal layer, and at least one flip chip connection layer on said support layer; and

at least one flip chip bump deposited on said flip chip connection layer over said active circuit.