Dual analog-to-digital converter system for increased dynamic range

• US 6,683,552 B2
• Filed: 12/17/2001
• Issued: 01/27/2004
• Est. Priority Date: 07/17/2001
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Bunch, Brian P., Noll, John M., Murthy, Sundara
• Primary Examiner(s): JeanGlaude, Jean Bruner
• Application Number:
  US10/024,100
• Publication Number:
  US 20030016150A1
• Time in Patent Office: 771 Days
• Field of Search: 341/139, 341/135, 341/131, 341/255, 342/92, 348/255, 600/364
• US Class Current: 341/155
• CPC Class Codes: H03M 1/188 Multi-path, i.e. having a separate analogue/digital converter for each possible range

Abstract

A dual analog-to-digital (A/D) converter circuit having two separate channels coupled to receive a single analog input signal, each of the two channels includes a means for converting an analog input signal to a digital signal at respective sample times that are adjustable to be substantially simultaneous; a means for adjusting the gain of the two channels to differ by a predetermined factor; a means for detecting a channel overflow condition in one of the two channels having a higher gain; and a means for merging the two channels into a continuous output stream.

Claims

1. A dual channel analog-to-digital converter circuit, comprising:

two separate channels each being coupled to receive a same analog input signal, each of the two channels having a means for converting an analog input signal to a digital signal at respective sample times that are adjustable to be substantially simultaneous;

a means for adjusting gain of both of the two channels to differ by a fixed multiplication factor;

a means for detecting a channel overflow condition in one of the two channels having a higher gain; and

a means for selecting one of the two channels.

2. The circuit of claim 1, further comprising a means for eliminating signal offset errors in the two channels.

3. The circuit of claim 2 wherein the means for eliminating signal offset errors further comprises a digital subtraction circuit.

4. The circuit of claim 1 wherein the means for selecting one of the two channels is operable as a function of a result generated by the channel overflow condition detecting means.

5. The circuit of claim 1 wherein the means for selecting one of the two channels is operable to output a result of the channel having lower gain when a channel overflow condition is detected on the channel having higher gain.

6. The circuit of claim 1, further comprising a means for matching a result of the channel having higher gain to a result of the channel having lower gain.

7. The circuit of claim 1 wherein the means for adjusting the gain of the two channels further comprises an amplifier circuit in each of the two channels.

8. The circuit of claim 1, further comprising a means for adjusting placement of a rising edge in a clock circuit portion of one channel in time with respect to a clock circuit portion of another channel.

9. The circuit of claim 1 wherein the channel overflow condition detecting means further comprises a digital comparator circuit.

10. A dual channel analog-to-digital converter circuit, comprising:

two separate channels each being coupled to receive a same analog input signal, each of the two channels having a means for converting an analog input signal to a digital signal at respective sample times that are adjustable to be substantially simultaneous;

a means for adjusting gain of both of the two channels to differ by a fixed multiplication factor;

a means for detecting a channel overflow condition in one of the two channels having a higher gain;

a means for selecting one of the two channels; and

a means for merging the two channels comprising a means for adjusting a data bit position of a result of the channel having lower gain to match a result of the channel having higher gain.

11. A dual analog-to-digital converter circuit, comprising:

first and second separate amplifier circuits each structured to receive a same analog input signal, the first amplifier circuit having a first gain and the second amplifier circuit having a second gain that is a fixed multiple of the first gain;

first and second analog-to-digital converters coupled respectively to sample an output of the first and second amplifier circuits and structured to output respective first and second digital signals representative of the analog input signal;

a comparator circuit coupled to the output of the first analog-to-digital converter and structured to detect a data overflow;

a first shift function coupled to the output of the second analog-to-digital converter and structured to left-shift data output by the second analog-to-digital; and

a multiplexer circuit coupled receive the output of the first amplifier circuit, an output of the comparator circuit and an output of the shift function, the multiplexer circuit being structured to select between the output of the first amplifier circuit and the output of the shift function as a function of the output of the comparator circuit and to merge the output of the first amplifier circuit and the output of the shift function into a continuous output stream.

12. The circuit of claim 11 wherein the fixed multiple is an even number.

13. The circuit of claim 11 wherein the fixed multiple is approximately four.

14. A dual analog-to-digital converter circuit, comprising:

first and second separate amplifier circuits each structured to receive a same analog input signal, the first amplifier circuit having a first gain and the second amplifier circuit having a second gain that is a fixed multiple of the first gain,

first and second analog-to-digital converters coupled respectively to sample an output of the first and second amplifier circuit and structured to output respective first and second digital signals representative of the analog input signal;

a clock circuit coupled to each of the first and second analog-to-digital converters and being structured to trigger the first and second analog-to-digital converters substantially simultaneously;

a comparator circuit/coupled to the output of the first analog-to-digital converter and structured to detect a data/overflow;

a first shift function coupled to the output of the second analog-to-digital converter and structured to left-shift data output by the second analog-to-digital; and

a multiplexer circuit coupled receive the output of the first amplifier circuit, an output of the comparator circuit and an output of the shift function, the multiplexer circuit being structured to select between the output of the first amplifier circuit and the output of the shift function as a function of the output of the comparator circuit and to merge the output of the first amplifier circuit and the output of the shift function into a continuous output stream.

15. A dual analog-to-digital converter circuit, comprising:

first and second amplifier circuits each structured to receive a same analog input signal, the first amplifier circuit having a first gain and the second amplifier circuit having a second gain that is higher than the first gain;

first and second analog-to-digital converters coupled respectively to sample an output of the first and second amplifier circuits and structured to output respective first and second digital signals representative of the analog input signal;

a clock circuit coupled to each of the first and second analog-to-digital converters and being structured to trigger the first and second analog-to-digital converters substantially simultaneously, the clock circuit further comprising;

first and second differential receivers each being structured to receive a same clock signal, one of the first and second differential receivers utilizing a variable threshold voltage to adjust placement of a rising edge in time with respect to another of the first and second differential receivers, and

first and second sample clocks receiving an output of the respective first and second differential receivers, the first and second sample clocks being structured to output sample timing signals to the first and second analog-to-digital converters, respectively;

a comparator circuit coupled to the output of the first analog-to-digital converter and structured to detect a data overflow;

a first shift function coupled to the output of the second analog-to-digital converter and structured to left-shift data output by the second analog-to-digital converter; and

a multiplexer circuit coupled receive the output of the first amplifier circuit, an output of the comparator circuit and an output of the shift function, the multiplexer circuit being structured to select between the output of the first amplifier circuit and the output of the shift function as a function of the output of the comparator circuit and to merge the output of the first amplifier circuit and the output of the shift function into a continuous output stream.

16. A dual analog-to-digital converter circuit, comprising:

first and second amplifier circuits each structured to receive a same analog input signal, the first amplifier circuit having a first gain and the second amplifier circuit having a second gain that is higher than the first gain;

first and second analog-to-digital converters coupled respectively to sample an output of the first and second amplifier circuits and structured to output respective first and second digital signals representative of the analog input signal;

a comparator circuit coupled to the output of the first analog-to-digital converter and structured to detect a data overflow;

a first shift function coupled to the output of the second analog-to-digital converter and structured to left-shift data output by the second analog-to-digital;

a multiplexer circuit coupled receive the output of the first amplifier circuit, an output of the comparator circuit and an output of the shift function, the multiplexer circuit being structured to select between the output of the first amplifier circuit and the output of the shift function as a function of the output of the comparator circuit and to merge the output of the first amplifier circuit and the output of the shift function into a continuous output stream; and

first and second subtraction circuits coupled respectively between the first and second analog-to-digital converters and the multiplexer circuit, the first and second subtraction circuits being structured to subtract from the result of the respective first and second analog-to-digital converters a fractional offset correction value.

17. The circuit of claim 16, further comprising a multiplication circuit coupled between the second subtraction circuit and the multiplexer circuit, the multiplication circuit being structured to fractionally scale the output of the second analog-to-digital converter by a predetermined factor to match the output of the first analog-to-digital converter.

18. A dual analog-to-digital converter circuit, comprising:

first and second separate amplifier circuits each structured to receive a same analog input signal, the first amplifier circuit having a first gain and the second amplifier circuit having a second gain that is a fixed multiple of the first gain;

first and second analog-to-digital converters coupled respectively to sample an output of the first and second amplifier circuits and structured to output respective first and second digital signals representative of the analog input signal;

a comparator circuit coupled to the output of the first analog-to-digital converter and structured to detect a data overflow;

a first shift function coupled to the output of the second analog-to-digital converter and structured to left-shift data output by the second analog-to-digital;

a multiplexer circuit coupled receive the output of the first amplifier circuit, an output of the comparator circuit and an output of the shift function, the multiplexer circuit being structured to select between the output of the first amplifier circuit and the output of the shift function as a function of the output of the comparator circuit and to merge the output of the first amplifier circuit and the output of the shift function into a continuous output stream; and

a second comparator circuit coupled to the output of the second analog-to-digital converter and structured to detect a data overflow and output an overflow signal comprising the data overflow.

19. An analog-to-digital converter circuit, comprising:

(a) an input port for receiving an analog input signal,

(b) a first channel having;

(i) a first buffer amplifier coupled to the input port and having a first gain,

(ii) a first analog-to-digital converter receiving an output of the first buffer amplifier, and

(iii) a shift function receiving a result of the first analog-to-digital converter;

(c) a second channel having;

(i) a second buffer amplifier coupled to the input port and having a second gain that is a fixed multiple of the first gain,

(ii) a second analog-to-digital converter receiving an output of the second buffer amplifier, and

(iii) a data overflow detection circuit receiving a result of the second analog-to-digital converter; and

(d) a multiplexing circuit coupled to receive a result of each respective first and second channels and to receive a result of the overflow detection circuit, the multiplexing circuit being structured to select the result of one of the first and second channels as a function of the result of the overflow detection circuit and to merge the selected results into a continuous output stream.

20. The circuit of claim 19 wherein the second gain is higher than the first gain by a predetermined factor.

21. The circuit of claim 19 wherein the second analog-to-digital converter is substantially identical to the first analog-to-digital converter.

22. The circuit of claim 19 wherein each of the first and second channels further comprises an offset correction circuit coupled between the respective first and second analog-to-digital converters and the multiplexing circuit.

23. The circuit of claim 19 wherein the shift register left-shifts data in the result of the first channel to match the result of the second channel before the result of the first channel is applied to the multiplexing circuit.

24. An analog-to-digital converter circuit, comprising:

(a) an input port for receiving an analog input signal,

(b) a first channel having;

(i) a first buffer amplifier coupled to the input port and having a first gain,

(ii) a first analog-to-digital converter receiving an output of the first buffer amplifier, and

(iii) a shift function receiving a result of the first analog-to-digital converter;

(c) a second channel having;

(i) a second buffer amplifier coupled to the input port and having a second gain that is a fixed multiple of the first gain,

(ii) a second analog-to-digital converter receiving an output of the second buffer amplifier, and

(iii) a data overflow detection circuit receiving a result of the second analog-to-digital converter;

(d) a clock circuit coupled to each of the first and second analog-to-digital converters, the clock circuit being structured to trigger the first and second analog-to-digital converters substantially simultaneously; and

(e) a multiplexing circuit coupled to receive a result of each respective first and second channels and to receive a result of the overflow detection circuit, the multiplexing circuit being structured to select the result of one of the first and second channels as a function of the result of the overflow detection circuit and to merge the selected results into a continuous output stream.

25. An analog-to-digital converter circuit, comprising:

(a) an input port for receiving an analog input signal,

(b) a first channel having;

(i) a first buffer amplifier coupled to the input port and having a first gain,

(ii) a first analog-to-digital converter receiving an output of the first buffer amplifier, and

(iii) a shift function receiving a result of the first analog-to-digital converter;

(c) a second channel having;

(i) a second buffer amplifier coupled to the input port and having a second gain that is a fixed multiple of the first gain,

(ii) a second analog-to-digital converter receiving an output of the second buffer amplifier, and

(iii) a data overflow detection circuit receiving a result of the second analog-to-digital converter;

(d) a multiplexing circuit coupled to receive a result of each respective first and second channels and to receive a result of the overflow detection circuit, the multiplexing circuit being structured to select the result of one of the first and second channels as a function of the result of the overflow detection circuit and to merge the selected results into a continuous output stream; and

a multiplying circuit coupled between the second analog-to-digital converter and the multiplexing circuit, the multiplying circuit being structured to scale the result of the second channel to match the result of the first channel.

26. A method for converting an analog signal to a digital signal, the method comprising:

splitting an input analog signal into large and small signal channels;

scaling the input signal on both the large and small signal channels such that the small signal channel has a higher resolution than the large signal channel by amplifying the input signal on the large signal channel with a first gain and amplifying the input signal on the small signal channel with a second gain that is higher than the first gain by a fixed multiplication factor;

sampling the large and small signal channels using separate analog-to-digital converters; and

outputting a result of one of the large and small signal channels as a function of determining whether the small signal channel is valid.

27. The method of claim 26 wherein sampling the large and small signal channels using analog-to-digital converters further comprises sampling the large and small signal channels substantially simultaneously.

28. The method of claim 26 wherein amplifying the input signal on each of the large and small signal channels further comprises buffering the input signal.

29. The method of claim 26, further comprising eliminating signal offset errors in the large and small signal channels.

30. A method for converting an analog signal to a digital signal, the method comprising:

splitting an input analog signal into large and small signal channels;

scaling the input signal on both the large and small signal channels such that the small signal channel has a higher resolution than the large signal channel by amplifying the input signal on the large signal channel with a first gain and amplifying the input signal on the small signal channel with a second gain that is higher than the first gain by a fixed multiplication factor;

sampling the large and small signal channels using separate analog-to-digital converters;

outputting a result of one of the large and small signal channels as a function of determining whether the small signal channel is valid;

merging a result of the large signal channel with a result of the small signal channel into a merged result; and

outputting the merged results.

31. The method of claim 30, further comprising adding precision to the result of the large signal channel.

32. The method of claim 31 wherein adding precision to the result of the large signal channel further comprises left-shifting the result.