Nonvolatile memory system, semiconductor memory, and writing method

• US 6,683,811 B2
• Filed: 03/17/2003
• Issued: 01/27/2004
• Est. Priority Date: 07/09/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/388,444
• Publication Number:
  US 20030156459A1
• Time in Patent Office: 316 Days
• Field of Search: 365/185.24, 365/185.18, 365/185.22, 365/185.29, 365/185.33, 365/185.02
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory apparatus comprising:

a controller; and

a plurality of memory devices,

wherein each of said memory devices includes a plurality of memory cells and a plurality of word lines, each of said word lines couples to corresponding ones of said memory cells,

wherein each of said memory cells has a threshold voltage within a plurality of threshold voltage ranges, one of which indicates an erase range and another indicates a program range,

wherein said controller is capable of issuing a plurality of commands to said memory devices, which commands include a first program command and a second program command,

wherein in an operation of said first program command, said memory device receives said first program command from said controller with a first data, selects one of said word lines and stores said first data to the memory cells coupled to said selected word line, and

wherein in an operation of said second program command, said memory device receives said second program command from said controller with a second data, selects one of said word lines, brings said threshold voltage of the memory cells coupled to said selected word line to said erase range and stores said second data to said memory cells coupled to said selected word line.

2. A nonvolatile memory apparatus according to claim 1,

wherein in said operation of said second program command, said memory device reads out data from said memory cells to a latch circuit before bringing said threshold voltage to said erase range, merges said read data and said second data and stores said merged data to said memory cells.

3. A nonvolatile memory apparatus according to claim 2, wherein said read data includes management data.

4. A nonvolatile memory apparatus according to claim 3, wherein said read data further includes operating system information.

5. A nonvolatile memory apparatus comprising:

a controller; and

a memory device;

wherein said memory device comprises a plurality of word lines and a plurality of memory cells, each of said word lines couples to corresponding ones of said memory cells, and each of said memory cells has a threshold voltage within a plurality of threshold voltage ranges, one of which is assigned with an erase range and another of which is assigned with a program range,

wherein first ones of said memory cells coupled to one of said word lines is capable of storing management data, and second ones of said memory cells coupled to said word line is capable of storing user data,

wherein said controller is capable of issuing a first program command and a second program command,

wherein in an operation of said first program command, said memory device receives first data with said first program command, selects one word line, reads said management data from said first ones of said memory cells coupled to said selected word line, brings said threshold voltage of said ones of said memory cells to said erase range, stores said management data to said first ones of said memory cells and stores said first data to said second ones of said memory cells, and

wherein in an operation of said second program command, said memory device receives second data with said second program command, selects one word line, and stores said second data to said memory cells coupled to said selected word line.

6. A nonvolatile memory apparatus comprising:

a controller; and

a memory device,

wherein said memory device comprises a plurality of memory cells and a plurality of word lines, each of said word lines couples to corresponding ones of said memory cells, and each of said memory cells has a threshold voltage within a plurality of threshold voltage ranges,

wherein first ones of said memory cells coupled to a first word line are capable of storing operating system information and second ones of said memory cells coupled to said first word line are capable of storing user data,

wherein said controller is capable of issuing a program command for storing data to said second ones of said memory cells coupled to said first word line, and

wherein in an operation of said program command for storing to said first word line, said memory device receives first data with said program command, selects said first word line, reads said operating system information from said first ones of said memory cells coupled to said first word line, erases data stored in said first ones of said memory cells coupled to said first word line, and stores said operating system information to said first ones of said memory cells and said first data to said second ones of said memory cells.

7. A nonvolatile memory apparatus according to claim 6,

wherein third ones of said memory cells coupled to a second word line are capable of storing management data, and fourth ones of said memory cells coupled to said first word line are capable of storing user data,

wherein said controller is capable of issuing said program command for storing data to said fourth ones of said memory cells coupled to said second word line, and

wherein in said operation of said program command for storing to said second word line, said memory device receives second data with said program command, selects said second word line, reads said management data from said third ones of said memory cells coupled to said second word line, erases data stored in said third ones of said memory cells coupled to said second word line, and stores said management data to said third ones of said memory cells and said second data to said fourth ones of said memory cells.

8. A nonvolatile memory apparatus according to claim 7,

wherein said first ones of said memory cells coupled to said first word line includes said third ones of said memory cells, and

wherein in said operation of said program command for storing to said first word line, said memory device receives said first data, selects said first word line, read said operating system information from said first ones of said memory cells and management data from said third ones of said memory cells, erases data stored in said first and third ones of said memory cells coupled to said first word line, and stores said operating system information to said first ones of said memory cells, said management data to said third ones of said memory cells, and said second data to said second ones of said memory cells.