Direct memory swapping between NAND flash and SRAM with error correction coding

• US 6,683,817 B2
• Filed: 02/21/2002
• Issued: 01/27/2004
• Est. Priority Date: 02/21/2002
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Li, Tao, Higgins, Richard, Wei, Jian, Arceo, Julio, Meagher, Bruce, Husseini, Jalal, Oishi, Moto, Rodrigues, Brian, Kang, Inyup
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/081,503
• Publication Number:
  US 20030156454A1
• Time in Patent Office: 705 Days
• Field of Search: 365/230.03, 365/235, 365/238.5, 365/185.11, 365/185.12, 365/185.33
• US Class Current: 365/230.03
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

Claims

1. A memory system for a wireless communication device comprising:

a static random access memory (SRAM) storage unit operative to provide storage of data;

a NAND Flash storage unit operative to provide additional storage of data;

an interface unit implemented within an application specific integrated circuit (ASIC) and operative to provide control signals for the SRAM and NAND Flash storage units; and

a data bus coupled to the SRAM and NAND Flash storage units and the interface unit, wherein the SRAM and NAND Flash storage units are implemented external to the ASIC, and wherein each storage unit is operable to concurrently store data from the other storage unit via the data bus when the other unit is accessed by the interface unit;

the interface unit being operable to receive a page address for the NAND Flash storage unit and a start address for the SRAM storage unit for a data transfer between the SRAM and NAND Flash storage units, and

operative to provide the control signals for the SRAM and NAND Flash storage units to effectuate the data transfer in response to receiving a start command.

3. The memory system of claims 1 or 2, wherein the interface unit includes an error correction coding (ECC) unit operative to perform block coding of data transferred to or from the NAND Flash storage unit.

4. The memory system of claim 3, wherein the ECC unit is operative to perform block coding of data based on a Hamming code.

5. The memory system of claim 1 or 2 wherein the interface unit includes an address generator operative to provide addresses for data transferred to or from the SRAM storage unit.

7. The memory system of claim 1 or 2, wherein the wireless communication device is a terminal in a wireless communication system.

8. The memory system of claims 1 or 2, wherein the wireless communication device is a cellular phone in a wireless communication system.

2. A memory system for a wireless communication device, comprising:

a static random access memory (SRAM) storage unit operative to provide storage of data;

a NAND Flash storage unit operative to provide additional storage of data;

an interface unit implemented within an application specific integrated circuit (ASIC) and operative to provide control signals for the SRAM NAND Flash storage units; and

a data bus coupled to the SRAM and NAND Flash storage units and the interface unit, wherein the SRAM and NANT) flash storage units are implemented external to the ASIC, and wherein each storage unit is operable to concurrently store data from the other storage unit via the data bus when the other storage unit is accessed by the interface unit;

wherein n write enable control for the SRAM is coupled to a read enable control for the NAND Flash, and wherein the write enable control for the NAND Flash is coupled to the read enable control for the SRAM.

6. The memory system of claim 2, wherein the interface unit is operable to receive page address for the NAN) Flash storage unit a start address fir the SRAM storage unit for a data transfer between the SRAM an NAND Flash storage units.

9. A method for transferring data between to storage units in a wireless communication device comprising:

receiving a start address for an SRAM storage unit;

receiving a page address for a NAND Flash storage unit;

providing control signals for the SRAM and NAND Flash storage units in response to receiving a start command;

retrieving data from a source storage unit via a data bus, wherein the source storage unit is either the SRAM or NAND Flash storage unit; and

writing the retrieved data to a destination storage unit via the data bus concurrently with the reading of the data from the source storage unit, wherein the destination storage unit is the other storage unit that is not the source storage unit.

10. The method of claim 9, further comprising:

generating an error correction code (ECC) value for each page of data transferred to or from the NAND Flash storage unit.

11. The method of claim 10, wherein a page of data is transferred from the NAND Flash storage unit to the SRAM storage unit, the method further comprising:

retrieving an ECC value stored in the NAND Flash storage unit for the data page retrieved from the NAND Flash; and

comparing the retrieved ECC value to the generated ECC value for the retrieved data page to determine whether or not there are any errors in the data page.

12. The method of claim 11, further comprising:

if there are errors in the retrieved data page,

identifying error bytes in the retrieved data page,

correcting the error bytes based on the retrieved ECC value, and

writing the corrected bytes to the SRAM storage unit.

13. A The method of claim 10, wherein a page of data is transferred from the SRAM storage unit to the NAND Flash storage unit, method further comprising:

writing the ECC value generated for the page to the NAND Flash storage unit.

14. A memory communicatively coupled to a digital signal processing device (DSPD) capable of interpreting digital information to:

receive a start address for an SRAM storage unit;

receive a page address for a NAND Flash storage unit;

receive a start command for a page transfer operation;

provide control signals for the SRAM and NAND Flash storage units in response to the start command;

retrieve data from a source storage unit via a data bus, wherein the source storage unit is either the SRAM or NAND Flash storage unit; and

write the retrieved data to a destination storage unit the data bus concurrently with the reading of the data from the source storage unit, wherein the destination storage unit is the other storage unit that is not the so storage unit.

15. The memory of claim 14, wherein the DSPD further capable of interpreting digital information to:

generate an error correction code (ECC) value for each page of data transferred to or from the NAND Flash storage unit.

16. The memory of claim 15, wherein a page of data is transferred from the NAND Flash storage unit to the SRAM storage unit, and wherein the DSPD is further capable of interpreting digital information to:

retrieve an ECC value stored in the NAND Flash storage for the data page retrieved from the NAND Flash; and

compare the retrieved ECC value to the generated ECC value for the retrieved data page to determine whether not there any error page.

17. The memory of claim 15, wherein the DSPD further capable of interpreting digital information to:

if there are errors in the retrieved data page,

identify error bytes in the retrieved data page,

correct the error bytes based an the retrieved ECC value, and

write the corrected bytes to the SRAM storage unit.

18. The memory of claim 15, wherein a page of data is transferred from the SRAM storage unit to the NAND Flash storage unit, and wherein the DSPD is further capable of interpreting digital information to:

write the ECC value generated for the data page to the NAND Flash storage unit.