Method and system for implementing an improved DSO switching capability in a data switch

• US 6,683,869 B1
• Filed: 12/02/1999
• Issued: 01/27/2004
• Est. Priority Date: 12/02/1999
• Status: Expired due to Fees

• Current Assignee: Verizon Patent and Licensing Incorporated (Verizon Communications Inc.)
• Original Assignee: WorldCom, Inc. (Verizon Communications Inc.)
• Inventors: Pierson, Forrest L. Jr.
• Primary Examiner(s): Ton, Dang
• Assistant Examiner(s): ABELSON, RONALD B
• Application Number:
  US09/452,956
• Time in Patent Office: 1,517 Days
• Field of Search: 370/351-356, 370/389, 370/392
• US Class Current: 370/352
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections

Abstract

A system and method for moving voice telephone calls through a data network. More particularly, the system and method are directed to the efficient operation of a novel port card for installation in present and future versions of data switches. Together port cards and data switches form nodes. The port card receives and transmits out signals through respective ports connected to links between nodes. The method provides for voice data to be switched in a Ds0 switching matrix, which is resident on the port card.

Claims

1. A communications network comprising:

at least two nodes connected to links, each of said nodes including;

a data switch having a data switching matrix,

a data bus connected to said data switch, and

at least one port card connected to said data bus, said port card including;

a high speed data bus,

an input system connected to the high speed data bus and one of said links,

an output system connected to the high speed data bus and one of said links, and

a Ds0 switch connected to said high speed data bus, said Ds0 switch including a Ds0 switching matrix; and

wherein said Ds0 switching matrix disassembles and reassembles packets after receipt of the packet by the port card from at least one of another data switch and said data switching matrix connected to said data bus,

wherein said input system includes a packet processor connected to said high speed data bus, said packet processor assigning a modifiable flag to each received packet to route the received packet through said node, and

said output system includes a packet inserter connected to said high speed data bus, said packet inserter removing the modifiable flag from each packet prior to the packet being sent to one of said links; and

wherein said modifiable flag allows said high speed bus to route the packet to said Ds0 switch to move Ds0 channels within the packet through said communications network.

2. The communications network according to claim 1, wherein said port card further includes:

a data switch interface connected to said high speed data bus and said data bus.

4. The communications network according to claim 1, wherein said Ds0 switch further includes

a packet disassembler connected to said high speed data bus and said Ds0 switching matrix, and

a packet assembler connected to said high speed data bus and said Ds0 switching matrix.

5. The communications network according to claim 4, wherein said Ds0 switching matrix includes

a data RAM connected to said packet disassembler and said packet assembler, and

a control RAM connected to said data RAM.

6. The communications network according to claim 1, wherein

said data switch further includes a control system in communication with said data switching matrix, and

said port card further includes a port control system connected to said high speed data bus, and said port control system is in communication with said control system of said data switch.

3. A communications network comprising:

at least two nodes, each of said nodes connected to at least one link and each node including;

a data switch having a data switching matrix,

a data bus connected to said data switch, and

at least one port card connected to said data bus, said port card including;

a high speed data bus,

an input system connected to the high speed data bus and one of said links,

an output system connected to the high speed data bus and one of said links,

a Ds0 switch connected to said high speed data bus, said Ds0 switch including a Ds0 switching matrix, wherein said Ds0 switching matrix disassembles and reassembles packets after receipt of the packet by the port card from at least one of another data switch and said data switching matrix connected to said data bus, and

a test circuit connected to said high speed data bus and at least one loopback path connecting said output system with said input system such that said test circuit and said loopback path test and verify data paths on said port card.

7. A communications network node comprising:

a data switch, said data switch including a data switching matrix,

a data bus connected to said data switch, and

at least two port cards connected to said data bus, each of said at least two port cards including;

a high speed data bus,

a Ds0 switch connected to said high speed data bus, said Ds0 switch including a Ds0 switching matrix,

an intake system coupled to said high speed data bus, said intake system configured to receive a signal with packets from a source external to said communications network node and said intake system comprising;

a packet processor coupled to said high speed data bus, said packet processor configured to assign a modifiable flag to each received packet to route the received packet through said communications network node, said modifiable flag being used to route the packet to said Ds0 switch via the high speed data bus, and

an outgoing system coupled to said high speed data bus, said outgoing system configured to transmit a signal with packets to a source external to said communications network node, said outgoing system comprising;

a packet inserter connected to said high speed data bus, said packet inserter configured to remove the modifiable flag from each packet prior to the packet being transmitted out of said communications network node; and

wherein said Ds0 switching matrix disassembles and reassembles packets with Ds0 channels after receipt of the packet by the port card from at least one of a source other than said data switch and from said data switching matrix connected to said data bus.

8. The communications network node according to claim 7, wherein said port card further includes:

a data switch interface connected to said high speed data bus and said data bus.

10. The communications network node according to claim 7, wherein said Ds0 switch further includes

a packet disassembler connected to said high speed data bus and said Ds0 switching matrix, and

a packet assembler connected to said high speed data bus and said Ds0 switching matrix.

11. The communications network node according to claim 10, wherein said Ds0 switching matrix includes

a data RAM connected to said packet disassembler and said packet assembler, and

a control RAM connected to said data RAM.

12. The communications network node according to claim 7, wherein

said data switch further includes a control system in communication with said data switching matrix, and

said port card further includes a port control system connected to said high speed data bus, and said port control system is in communication with said control system of said data switch.

9. A communications network node comprising:

a data switch, said data switch including a data switching matrix,

a data bus connected to said data switch, and

at least two port cards connected to said data bus, each of said at least two port cards including;

a high speed data bus,

a Ds0 switch connected to said high speed data bus, said Ds0 switch including a Ds0 switching matrix,

an intake system coupled to said high speed data bus, said intake system configured to receive a signal with packets from a source external to said communications network node,

an outgoing system coupled to said high speed data bus, said outgoing system configured to transmit a signal with packets to a source external to said communications network node, and

a test circuit connected to said high speed data bus and at least one loopback path connecting said outgoing system with said intake system such that said test circuit and said loopback path test and verify data paths on said port card; and

wherein said Ds0 switching matrix disassembles and reassembles packets with Ds0 channels after receipt of the packet by the port card from at least one of a source other than said data switch and from said data switching matrix connected to said data bus.

13. A port card comprising:

a high speed data bus,

an intake system connected to said high speed data bus,

an outgoing system connected to said high speed data bus,

a port control system connected to said high speed data bus,

a switch interface connected to said high speed data bus,

a Ds0 switch connected to said high speed data bus, wherein said Ds0 switch disassembles and reassembles packets after initial receipt of the packet by at least one of said intake system and said switch interface based on the packet,

a control bus connected to at least one of said intake system, said outgoing system, said switch interface, and said Ds0 switch,

a test circuit connected to said high speed data bus and said control bus, and

at least one loopback path connecting said outgoing system with said intake system, said test circuit and said loopback path being configured to test and verify data paths on said port card.

14. The port card according to claim 13, wherein the control bus is connected to each of said intake system, said outgoing system, said switch interface, and said Ds0 switch.

15. A port card comprising:

a high speed data bus,

a port control system coupled to said high speed data bus,

a switch interface coupled to said high speed data bus,

a Ds0 switch coupled to said high speed data bus,

an intake system coupled to said high speed data bus, said intake system comprising;

a packet processor connected to said high speed data bus, said packet processor configured to assign a modifiable flag to each received packet to route the received packet through said port card, and

an outgoing system coupled to said high speed data bus, said outgoing system comprising;

a packet inserter connected to said high speed data bus, said packet inserter configured to remove the modifiable flag from each packet prior to the packet being transmitted by said port card, wherein said modifiable flag is used to route the packet to said Ds0 switch and move Ds0 channels as part of packets through a communications network, and

wherein said Ds0 switch disassembles and reassembles packets after initial receipt of the packet by at least one of said intake system and said switch interface based on the packet.

16. A port card comprising:

a high speed data bus,

an intake system connected to said high speed data bus,

an outgoing system connected to said high speed data bus,

a port control system connected to said high speed data bus,

a switch interface connected to said high speed data bus, and

a Ds0 switch connected to said high speed data bus and configured to disassemble and reassemble packets after initial receipt of the packet by at least one of said intake system and said switch interface based on the packet, the Ds0 switch comprising;

a Ds0 switching matrix,

a packet disassembler connected to said high speed data bus and said Ds0 switching matrix, and

a packet assembler connected to said high speed data bus and said Ds0 switching matrix; and

wherein said Ds0 switching matrix organizes Ds0 channels based at least in part on the destination of each Ds0 channel.

17. The port card according to claim 16, wherein said Ds0 switching matrix includes

a data RAM connected to said packet disassembler and said packet assembler, and

a control RAM connected to said data RAM.

18. A port card comprising:

means for receiving packets as at least one of a asynchronous transmission and a synchronous transmission, the means for receiving comprising;

means for accepting at least one signal having packets,

means for removing frame bits within the signal,

means for separating the remaining data bits left within the signal into individual packets, and

means for attaching a flag to each packet, wherein the flag is representative of internal addressing information and is modifiable,

means for transmitting packets as at least one of a asynchronous transmission and a synchronous transmission, the means for transmitting comprising;

means for removing the flag attached to each packet, and

means for preparing each packet for transmission,

means for interfacing with a data switch,

means for processing packets having Ds0 channels, and

means for routing information between said receiving means, said transmitting means, said interfacing means, and said processing means; and

wherein said routing means routes packets having Ds0 channels at least in part based on the respective packet to said processing means after receiving the respective packet from at least one of said receiving means and said interfacing means.

19. The port card according to claim 18, wherein said processing means includes

means for disassembling packets having Ds0 channels into bytes,

means for switching bytes around to form new packets, and

means for assembling the switched around bytes into new packets.

20. The port card according to claim 18, wherein the flag is modifiable by said processing means.

22. The port card according to claim 18, wherein said routing means is a high speed data bus.

23. The port card according to claim 18, wherein said processing means is a Ds0 switch.

24. The port card according to claim 18, wherein said receiving means and said transmitting means communicate using the same transfer mode type.

21. A port card comprising:

means for receiving packets as at least one of a asynchronous transmission and a synchronous transmission,

means for transmitting packets as at least one of a asynchronous transmission and a synchronous transmission,

means for interfacing with a data switch,

means for processing packets having Ds0 channels,

means for routing information between said receiving means, said transmitting means, said interfacing means, and said processing means, wherein said routing means routes packets having Ds0 channels at least in part based on the respective packet to said processing means after receiving the respective packet from at least one of said receiving means and said interfacing means,

means for controlling the operation of said port card, and

means for testing and verifying the data paths and functionality of said port card.

25. A telecommunications network switching method comprising:

receiving a signal at a communications node,

separating the signal into packets,

routing individual packets with Ds0 channels to a first Ds0 switch and switching the Ds0 channels into new packets headed to the same outgoing port of the communications node when the packet includes at least one Ds0 channel destined for another communications node,

routing packets based on their destination to the appropriate transmission port,

manipulating Ds0 channels of packets in a second Ds0 switch into at least one of larger packets, packets with more channels for fixed size packets, and packets destined for the same outgoing port at the next communications node, and

transmitting the packets as a signal to the next communications node.

26. The method according to claim 25, wherein the first Ds0 switch is on a first port card and the second Ds0 switch is on at least one of a second port card and the first port card.

27. The method according to claim 25, further comprising:

generating test packets in a test circuit,

routing the test packets through at least a portion of the communications node, and

verifying the path followed by the test packet and the switching functions are operating properly after the test packet returns to the test circuit.

28. The method according to claim 27, wherein routing the test packets includes

sending the test packets to any packet destination in the communications node, and

returning the test packets from any packet destination in the communications node to the test circuit.

29. The method according to claim 27, wherein routing the test packets includes

sending the test packets to the Ds0 switch,

looping the test packets repeatedly through the Ds0 switch to perform bit error rate testing, and

returning the test packets to the test circuit.

30. The method according to claim 25, further comprising:

transmitting a first type of control signals internal to the communications node through a data bus, and

transmitting a second type of control signals internal to the communications nodes through an out-of-band channel; and

wherein the first type of control signals includes signals distinct from signals included within the second type of control signals.

31. The method according to claim 30, wherein the first type of control signals includes configuration setup and statistical downloads.

32. The method according to claim 25, wherein said separating the signal into packets includes

removing the frame bits in the signal,

separating the remaining bits into packets, and

attaching a flag to each of the packets based on the respective packet.

33. The method according to claim 32, wherein the flag for internal addressing of the packet within the communications node and as such is modifiable within the communications node.

34. The method according to claim 32, wherein routing individual packets to a first Ds0 switch includes determining based on the flag whether Ds0 channels are included within the packet.

35. The method according to claim 32, wherein switching the Ds0 channels and manipulating Ds0 channels include

separating the Ds0 channels within each packet,

sorting the Ds0 channels based on the destination downstream communications node to which the Ds0 channel is addressed for,

organizing the sorted Ds0 channels into new packets, and

attaching a new flag to each new packet.

36. The method according to claim 32, wherein said transmitting includes

removing the attached flag from each packet,

creating the signal, and

sending the signal to the next communications node.

37. A method for operating a port card comprising:

receiving packets from a communications conduit,

routing each packet based on destination of that packet such that

when the packet includes at least two Ds0 channels destined for at least two different transmission ports, the packet is routed through a Ds0 switch,

when the packet includes only data, the packet is routed to a data switch, and

when all Ds0 channels in the packet are directed to the same downstream communications node, the packet is routed to a data switch,

interfacing with a data switch,

routing each packet received from the data switch to the Ds0 switch when the packet includes at least one of at least two Ds0 channels destined for different outgoing ports and the packet contains insufficient Ds0 channels, and

transmitting the packet into a communications conduit.

38. The method according to claim 37, wherein when a packet is routed through a Ds0 switch, said method includes

separating the Ds0 channels in the packet,

sorting the Ds0 channels based on the destination downstream communications node to which the Ds0 channel is addressed for,

organizing the sorted Ds0 channels into new packets.

39. The method according to claim 37, further comprising:

attaching a flag to each packet after receiving the packet,

striping the flag from each packet prior to transmitting the packet, and

wherein the flag represents internal addressing information regarding the respective packet and as such is modifiable as packets undergo modification and creation.

40. The method according to claim 37, further comprising testing the operation of the port card.

41. The method according to claim 40, wherein testing includes

generating a test packet,

routing the test packet through the port card,

verifying the path of the test packet and the operation of the port card based on the routed test packet.

42. The method according to claim 41, wherein routing the test packet includes looping the test packet through the Ds0 switch to perform bit error rate testing.

43. The method according to claim 37, further comprising determining whether insufficient Ds0 channels are in a packet based on whether additional Ds0 channels may be placed within the packet.

44. The method according to claim 37, further comprising determining whether insufficient Ds0 channels are in a packet based on the size of the packet in relation to the size of other packets such that when the packet is smaller than other packets, the packet will be combined with other packets.