Digital phase/frequency detector, and clock generator and data recovery PLL containing the same

• US 6,683,930 B1
• Filed: 12/23/1999
• Issued: 01/27/2004
• Est. Priority Date: 12/23/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dalmia, Kamal
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): WILLIAMS, LAWRENCE B
• Application Number:
  US09/470,665
• Time in Patent Office: 1,496 Days
• Field of Search: 331/11-25, 327/1-503
• US Class Current: 375/376
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses

Abstract

An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate a first output signal having a first data rate in response to an input signal having a second data rate and clock signal having the second data rate. The second circuit may be configured to generate a second output signal in response to the input signal and the clock signal. The logic circuit may be configured to generate a clock signal in response to the first output signal and the second output signal.

Claims

1. An apparatus comprising:

a phase detector circuit configured to generate a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate;

a frequency detector circuit configured to generate a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and

a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal.

2. The apparatus according to claim 1, wherein said phase detector circuit is further configured to generate a first recovered data signal having said second data rate.

3. The apparatus according to claim 1, wherein said phase detector circuit comprises a digital linear phase detector and said frequency circuit comprises a digital frequency detector.

4. The apparatus according to claim 2, wherein said first data signal comprises a re-timed data signal.

5. The apparatus according to claim 1, wherein said clock signal comprises a recovered clock signal.

6. The apparatus according to claim 1, wherein said first data rate, said second data rate and said third data rate are the same data rate or a different data rate.

7. The apparatus according to claim 1, wherein said first and said second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.

8. The apparatus according to claim 5, wherein (i) said first output signal and/or (ii) said second output signal is configured to control said logic circuit.

9. The apparatus according to claim 7, wherein said logic circuit comprises (i) a gate, (ii) a charge pump and filter circuit and (iii) a VCO, wherein said gate is configured to receive said first and second signals.

10. The apparatus according to claim 9, wherein said charge pump and said filter circuit are configured to control said VCO in response to said gate, wherein said VCO is configured to generate said clock signal.

11. The apparatus according to claim 9, wherein said gate (i) comprises a digital OR gate and (ii) is configured to digitally combine said first and second signals.

12. The apparatus according to claim 11, wherein said apparatus comprises a reference-less dual loop clock and data architecture.

21. The apparatus according to claim 1, wherein said apparatus comprises a reference-less dual loop clock and data architecture.

13. An apparatus comprising:

means for using a phase detector for generating a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate;

means for using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and

means for generating said clock signal in response to (i) said first output signal and (ii) said second output signal.

14. A method for clock data recovery comprising the steps of:

(A) using a phase detector for generating a first output signal having a first data rate in response to (i) data input signal having a second data rate and (ii) a clock signal having said second data rate;

(B) using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and

(C) generating said clock signal in response to (i) said first output signal and (ii) said second output signal.

15. The method according to claim 14, wherein step (A) further comprises the sub-step of:

(A-1) generating a first data signal having said second data rate.

16. The method according to claim 15, wherein said first data signal comprises a re-timed data signal.

17. The method according to claim 14, wherein said clock signal comprises a recovered clock signal.

18. The method according to claim 14, wherein said first and second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.

19. The method according to claim 14, wherein (i) said first and/or (ii) said second signal controls the generation of said clock signal.

20. The method according to claim 14, wherein said step (C) further comprises adding said first and second output signals.