Synchronous integrated circuit device

• US 6,684,285 B2
• Filed: 07/25/2002
• Issued: 01/27/2004
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US10/205,241
• Publication Number:
  US 20030005208A1
• Time in Patent Office: 551 Days
• Field of Search: 713/400, 713/401, 710/100, 710/305, 365/189.01, 365/189.02
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 : Control signal input circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

An integrated circuit device that includes a clock synchronization circuit. The clock synchronization circuit receives an external clock signal and generates an internal clock signal from the external clock signal using a feedback loop. The internal clock signal is adjusted based on feedback provided via the feedback loop. In addition, the integrated circuit device includes an output circuit. The output circuit includes an output driver to output at least two bits of data in succession during a clock cycle of the external clock signal. The data is output synchronously with respect to the internal clock signal.

Claims

1. An integrated circuit device, wherein the integrated circuit device comprises:

a clock circuit, including a feedback loop, to synchronize output of data by the integrated circuit device with an external clock signal, wherein the feedback loop generates a first clock signal having a timing relationship with the external clock signal, wherein the timing relationship is controlled based on a comparison between the first clock signal and the external clock signal; and

an output circuit coupled to the clock circuit, wherein the output circuit includes an output driver to output at least two bits of the data in succession during a clock cycle of the external clock signal.

2. The integrated circuit device of claim 1, wherein the feedback loop includes:

a first input sampler to generate a first feedback signal based on the comparison between the first clock signal and the external clock signal; and

a first variable delay line, coupled to the first input sampler, to generate a delayed clock signal, wherein the delayed clock signal has a delay, relative to the external clock signal, that is varied in response to the first feedback signal, wherein the first clock signal is derived from the delayed clock signal.

3. The integrated circuit device of claim 2, wherein, to perform the comparison between the external clock signal and the first clock signal, the first input sampler samples the external clock signal in response to a transition of the first clock signal.

4. The integrated circuit device of claim 2, further including an amplifier, coupled to the first variable delay line, to receive the external clock signal and provide an amplified version of the external clock signal to the first variable delay line.

5. The integrated circuit device of claim 2, wherein the clock circuit further includes;

a second input sampler to generate a second feedback signal based on a comparison between a second clock signal and an externally delayed version of the external clock signal;

a second variable delay line, coupled to the second input sampler and the first variable delay line, to generate the second clock signal, wherein the second clock signal has a delay relative to the delayed clock signal that is varied in response to the second feedback signal; and

a third variable delay line, coupled to the second input sampler and the first variable delay line, to generate a third clock signal using the delayed clock signal and the second feedback signal, wherein the output driver outputs a first bit of the at least two bits of the data in response to the third clock signal.

6. The integrated circuit device of claim 5, wherein the third clock signal is delayed with respect to the delayed clock signal such that the third clock signal transitions midway between transitions of the external clock signal and respective transitions of the externally delayed version of the external clock signal.

7. The integrated circuit device of claim 5, wherein the output circuit further includes a multiplexer coupled to the output driver and the clock circuit, the multiplexer to receive the third clock signal and provide the first bit of the at least two bits of the data to the output driver in response to the third clock signal.

8. The integrated circuit device of claim 1, wherein the output circuit further includes a multiplexer coupled to the output driver and the clock circuit, wherein the multiplexer provides a first bit of the at least two bits of the data to the output driver in response to a second clock signal generated by the clock circuit, wherein the second clock signal is generated using the delayed clock signal.

9. The integrated circuit device of claim 8, wherein the multiplexer provides a second bit of the at least two bits of the data to the output driver in response to a complementary version of the second clock signal generated by the clock circuit.

10. The integrated circuit device of claim 1, further including:

an array of dynamic memory cells; and

a plurality of sense amplifiers, coupled to the array of dynamic memory cells, wherein the at least two bits of the data are sensed using at least two sense amplifiers of the plurality of sense amplifiers.

11. The integrated circuit device of claim 10, further including:

a plurality of input receivers to sample an operation code using the external clock signal, wherein;

the operation code includes precharge information, wherein, in response to the precharge information, the plurality of sense amplifiers is automatically precharged after the at least two bits of the data are sensed; and

the operation code specifies a read operation, wherein the output driver outputs the at least two bits of the data in response to the operation code specifying the read operation; and

a plurality of internal data lines, coupled between the plurality of sense amplifiers and the output circuit, to transfer the at least two bits of the data from the at least two sense amplifiers for output by the output driver.

12. The integrated circuit device of claim 1 further including an array of static memory cells to store the at least two bits of the data.

13. The integrated circuit device of claim 1, wherein the integrated circuit device is a cross-point switch.

14. An integrated circuit device, comprising:

a clock synchronization circuit that includes a feedback loop, the clock synchronization circuit to receive an external clock signal and generate an internal clock signal from the external clock signal using the feedback loop, wherein the internal clock signal is adjusted based on feedback provided via the feedback loop; and

an output circuit including an output driver to output at least two bits of data in succession during a clock cycle of the external clock signal, wherein the data is output synchronously with respect to the internal clock signal.

15. The integrated circuit device of claim 14, wherein:

the clock synchronization circuit includes an amplifier to receive the external clock signal and generate an amplified clock signal; and

the feedback loop includes a variable delay line to receive the amplified clock signal and generate a delayed clock signal relative to the amplified clock signal such that the delayed clock signal includes a delay that is varied based on a comparison between a first clock signal and the external clock signal, wherein the first clock signal and the internal clock signal are generated using the delayed clock signal.

16. The integrated circuit device of claim 15, wherein the feedback loop further includes a fixed delay line, coupled to the variable delay line, to receive the delayed clock signal and output the first clock signal, wherein the first clock signal is generated by adding a predetermined amount of delay to the delay of the delayed clock signal using the fixed delay line.

17. The integrated circuit device of claim 16, further including:

a second delay line, coupled to the variable delay line, to receive the delayed clock signal and output a second clock signal; and

a third delay line, coupled to the variable delay line, to receive the delayed clock signal and output the internal clock signal such that the delay of the internal clock signal relative to the delayed clock signal is controlled based on a comparison between the second clock signal and a delayed version of the external clock signal.

18. The integrated circuit device of claim 17, wherein the delay of the internal clock signal is controlled such that the internal clock signal transitions midway between transitions of the external clock signal and corresponding transitions of the delayed version of the external clock signal.

19. The integrated circuit device of claim 14, further including an array of static memory cells, wherein the at least two bits of data are accessed from the array of static memory cells.

20. The integrated circuit device of claim 14, wherein the integrated circuit device is a cross-point switch.

21. The integrated circuit device of claim 14, wherein the integrated circuit device is a controller device that controls an operation of a synchronous memory device, wherein the output driver outputs the at least two bits of data to the memory device.

22. The integrated circuit device of claim 14, wherein the integrated circuit device further includes a multiplexer, coupled to the output driver and the clock synchronization circuit, wherein the multiplexer provides the at least two bits of data to the output driver in response to the internal clock signal.

23. The integrated circuit device of claim 14, further including:

a memory array having a plurality of dynamic memory cells; and

a plurality of sense amplifiers, coupled to the memory array, to sense the at least two bits of data from the dynamic memory cells.

24. The integrated circuit device of claim 23, further including:

a plurality of internal data lines, coupled between the plurality of sense amplifiers and the output circuit, to transfer data sensed by the plurality of sense amplifiers for output by the output circuit; and

a plurality of input receivers to sample an operation code that includes precharge information, wherein, in response to the precharge information, the plurality of sense amplifiers is automatically precharged after the at least two bits of data are sensed in the plurality of sense amplifiers.

25. The integrated circuit device of claim 24, wherein the operation code specifies a read operation, and wherein the output driver outputs the at least two bits of data in response to the operation code.

26. The integrated circuit device of claim 24, wherein the plurality of input receivers samples the operation code from an external bus, wherein the external bus is used to carry the operation code and the at least two bits of data.

27. The integrated circuit device of claim 26 wherein the external bus is used to carry the operation code and the at least two bits of data in a multiplexed format.

28. The integrated circuit device of claim 14, wherein a first bit of the at least two bits of data is output in response to the internal clock signal.

29. The integrated circuit device of claim 28 wherein a second bit of the at least two bits of data is output in succession to the first bit and in response to a clock signal that is complementary in phase to the internal clock signal.

30. A method of operation of an integrated circuit device comprising:

receiving an external clock signal;

generating an internal clock signal from the external clock signal using a circuit that includes a feedback loop, wherein generating includes adjusting a timing relationship between the internal clock signal and the external clock signal based on feedback provided by the feedback loop; and

outputting at least two bits of data in succession during a clock cycle of the external clock signal, wherein the at least two bits of data are output synchronously with respect to the internal clock signal.

31. The method of claim 30, wherein outputting the at least two bits of data further comprises outputting at least one bit of the at least two bits of data in response to a transition of the internal clock signal.

32. The method of claim 30, wherein adjusting the timing relationship between the internal clock signal and the external clock signal is performed based on additional feedback provided by a second feedback loop.

33. The method of claim 30, further including:

generating a delayed clock signal having a first delay with respect to the external clock signal;

delaying the delayed clock signal using a fixed delay to produce a first clock signal;

adjusting the first delay of the delayed clock signal based on the feedback provided by the feedback loop, wherein the feedback loop performs a comparison between the first clock signal and the external clock signal to produce the feedback;

generating a second clock signal having a second delay with respect to the delayed clock signal;

adjusting the second delay of the second clock signal based on a comparison between the second clock signal and an externally delayed version of the external clock signal; and

generating the internal clock signal from the delayed clock signal, wherein a timing relationship between the internal clock signal and the delayed clock signal is adjusted based on the comparison between the second clock signal and the externally delayed version of the external clock signal.

34. The method of claim 30, wherein the integrated circuit device includes a memory array having a plurality of memory cells, and wherein the method further includes sensing the at least two bits of data from the plurality of memory cells.

35. The method of claim 30, further including sampling an operation code specifying a read operation, wherein the at least two bits of data are output in response to the operation code specifying a read operation.

36. The method of claim 35, wherein the operation code includes precharge information, wherein the method further includes:

sensing, in a plurality of sense amplifiers, the at least two bits of data from a memory array having a plurality of dynamic random access memory cells, wherein the plurality of sense amplifiers and the memory array are included in the integrated circuit device; and

automatically precharging the plurality of sense amplifiers, in response to the precharge information, after sensing the at least two bits of data.

37. The method of claim 36, further including sampling address information that is used to identify the at least two bits of data within the plurality of dynamic random access memory cells.