Intermediate-grain reconfigurable processing device

• US 6,684,318 B2
• Filed: 11/12/2002
• Issued: 01/27/2004
• Est. Priority Date: 04/11/1996
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: DeHon, André, Knight, Thomas F. Jr., Mirsky, Ethan
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US10/293,887
• Publication Number:
  US 20030200418A1
• Time in Patent Office: 441 Days
• Field of Search: 712/15, 712/20, 712/33, 712/229
• US Class Current: 712/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus

Abstract

A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Claims

1. A programmable integrated circuit comprising:

a plurality of like functional units arranged to perform operations on data in response to instructions and to store configuration data, each functional unit including a first memory and an arithmetic and logic unit;

a plurality of second memories outside the functional units and in the integrated circuit;

a configurable first bus coupled to the functional units and arranged in a first configuration to transmit control commands from the functional units and arranged in a second configuration to transmit data from the functional units; and

a plurality of second busses coupled to the functional units and arranged to transmit data from the functional units to the second memories.

2. An integrated circuit as claimed in claim 1 wherein the second memories comprise registers.

3. An integrated circuit as claimed in claim 1 wherein the first bus is configured by changes to bits in the functional units.

4. In a programmable integrated circuit comprising a plurality of like functional units coupled by an interconnect, the functional units including memory and arithmetic and logic units, a method of processing data in the functional units and transmitting the data comprising:

storing data in the functional units;

performing arithmetic and logic operations in the functional units in response to instructions and in response to data stored in the functional units;

storing configuration data in the functional units;

storing data outside the functional units in the integrated circuit via transmission of the data from the functional units on the interconnect;

configuring the interconnect in a first configuration to transmit control commands from the functional units; and

configuring the interconnect in a second configuration to transmit data from the functional unbits.

5. A method as claimed in claim 4 wherein the integrated circuit comprises registers outside the functional units and in the integrated circuit, and wherein storing data outside the functional units in the integrated circuit comprises storing data in the registers.

6. A method as claimed in claim 4 wherein configuring the interconnect in a first configuration and configuring the interconnect in a second configuration comprises changing to bits in the functional units.