System for efficient operation of a very long instruction word digital signal processor

• US 6,684,319 B1
• Filed: 06/30/2000
• Issued: 01/27/2004
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: AIM IP, LLC
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Mohamed, Moataz A., Bindloss, Keith M.
• Primary Examiner(s): TSAI, HENRY
• Application Number:
  US09/608,233
• Time in Patent Office: 1,306 Days
• Field of Search: 712/24, 712/23, 712/26, 712/205, 712/204, 712/213, 712/210, 712/233, 712/241, 712/207, 711/100, 711/137, 711/213, 711/221
• US Class Current: 712/24
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks

Abstract

The present invention minimizes power consumption and processing time in a very long instruction word digital signal processor by identifying certain blocks of instructions and placing them in a small, fast buffer for subsequent retrieval and execution. A decoder unit decodes a prefetch instruction flag bit that indicates when instructions are to be prefetched and placed into the buffer. The decoder unit signals a control unit, which sends the instruction code from a memory unit to the buffer and maintains an address mapping table and a program counter. The control unit also sets a select input on a multiplexer to indicate that the multiplexer is to output the prefetch instructions it receives from the buffer. The multiplexer outputs the prefetch instructions to an instruction register that sends the prefetch instructions to appropriate functional units for execution.

Claims

1. A very long instruction word processing system, including a memory unit, a decoder unit, and an instruction register, wherein said system minimizes power consumption and processing time, said system comprising:

a prefetch instruction buffer, wherein said prefetch instruction buffer stores a plurality of prefetch instructions received from the memory unit;

a prefetch instruction flag bit, wherein said prefetch instruction flag bit is decoded by the decoder unit and said prefetch instruction flag bit indicates that said prefetch instructions are to be placed into said buffer;

a prefetch instruction control unit, wherein said control unit receives said prefetch instruction flag bit from the decoder unit and wherein said control unit facilitates the placement of said prefetch instructions into said buffer; and

a multiplexer, wherein said multiplexer receives a select input flag bit and said multiplexer outputs a plurality of instructions to the instruction register based on said select input flag bit.

2. The system of claim 1, wherein said prefetch instruction flag bit is set by a compiler.

3. The system of claim 1, wherein each of said prefetch instructions has a length selected from the group consisting of 128 bits and 256 bits.

4. The system of claim 1, wherein said buffer is configured to store a maximum of 32 prefetch instructions.

5. The system of claim 1, wherein said system further includes an instruction cache and wherein said multiplexer has a first input and a second input, wherein said first input is received from said prefetch instruction buffer and wherein said second input is received from said instruction cache.

6. The system of claim 5, wherein said control unit sets said select input flag bit to a first value indicating that said multiplexer is to output to the instruction register said first input.

7. The system of claim 5, wherein said control unit sets said select input flag bit to a second value indicating that said multiplexer is to output to the instruction register said second input.

8. The system of claim 5, wherein said instruction cache is multi-tiered into levels ranging from low to high and said buffer is smaller than the lowest level cache in size.

9. The system of claim 5, further comprising a terminate instruction, wherein said terminate instruction is decoded by the decoder unit, wherein said control unit receives said terminate instruction and sets said select input flag bit to a value indicating that said multiplexer is to output to the instruction register input received from the instruction cache.

10. The system of claim 1, further comprising an address mapping table, wherein said address mapping table includes an address in the memory unit of said prefetch instructions, a starting address in said buffer of said prefetch instructions, and an ending address in said buffer of said prefetch instructions, wherein said address mapping table is maintained by said control unit.

11. The system of claim 10, wherein said control unit comprises a movable program counter, wherein said movable program counter is initialized to said starting address and is incremented at a preset value until said movable program counter equals said ending address.

12. The system of claim 10, further including a repeat instruction, wherein said repeat instruction is decoded by the decoder unit and wherein said repeat instruction indicates that said prefetch instructions are to be placed into said prefetch instruction buffer.

13. The system of claim 10, wherein said control unit receives a repeat instruction, searches said address mapping table to determine if said prefetch instructions are in said buffer, locates said prefetch instructions in said buffer, re-initializes a movable program counter to said starting address, and sets said select input flag bit to a value indicating that said multiplexer is to output to the instruction register said prefetch instructions received from said buffer.

14. A very long instruction word digital signal processor including a memory unit, a decoder unit, an instruction cache, and instruction register, wherein said processor minimizes power consumption and processing time, said processor comprising:

a prefetch instruction buffer configured to contain a plurality of prefetch instructions received from the memory unit;

a prefetch instruction control unit, wherein said control unit receives a prefetch instruction flag bit from the decoder unit which indicates that said prefetch instructions are to be placed into said prefetch instruction buffer and wherein said control unit facilitates the placement of said prefetch instructions into said prefetch instruction buffer; and

a multiplexer, including a first input, a second input, a select input flag bit, and an output, wherein said first input is received from said prefetch instruction buffer, said second input is received from said instruction cache, said select input flag bit is set by said control unit and said output is transmitted to the instruction register based on said select input flag bit.

15. The processor of claim 14, wherein the instruction cache is multi-tiered into levels ranging from low to high and said buffer is smaller than the lowest level cache.

16. The processor of claim 14, wherein said control unit maintains an address mapping table, said address mapping table including an address in the memory unit of said prefetch instructions, a starting address in said buffer of said prefetch instructions, and an ending address in said buffer of said prefetch instructions.

17. The processor of claim 16, wherein said control unit maintains a movable program counter, wherein said movable program counter is initialized to said starting address and is incremented by a preset amount until said movable program counter equals said ending address.

18. A method for efficiently retrieving instructions in a digital processor, including a memory unit, a decoder unit, and instruction register, said method comprising the steps of:

decoding a prefetch instruction flag bit indicating that a plurality of prefetch instructions is to be placed into a prefetch instruction buffer;

transmitting to a prefetch instruction control unit said prefetch instruction flag bit;

searching said prefetch instruction buffer for said prefetch instructions;

transmitting to a multiplexer a first input of said prefetch instructions from said prefetch instruction buffer;

setting a select input flag bit in said control unit;

transmitting to said multiplexer said select input flag bit; and

transmitting an output from said multiplexer to the instruction register based on said select input flag bit.

19. The method of claim 18, further comprising the steps of:

copying said prefetch instructions from the memory unit to said prefetch instruction buffer; and

storing in an address mapping table an address in the memory unit of said prefetch instructions, a starting address in said buffer of said prefetch instructions, and an ending address in said buffer of said prefetch instructions, wherein said address mapping table is maintained by said control unit.

20. The method of claim 18, wherein said prefetch instructions have a length selected from the group consisting of 128 bits and 256 bits.

21. The method of claim 18, wherein said buffer is configured to store a maximum of 32 prefetch instructions.

22. The method of claim 18, wherein the processor further includes an instruction cache, said method further comprising the steps of:

decoding a terminate flag bit in the decoder unit;

transmitting a signal to said control unit said signal indicating that said terminate flag bit has been decoded;

transmitting to said multiplexer a second input from the instruction cache; and

setting said select input flag bit to a second value indicating that said output is to equal said second input.

23. The method of claim 18, wherein the processor further includes an instruction cache, wherein the instruction cache is multi-tiered into levels ranging from low to high and wherein said prefetch instruction buffer is smaller than the lowest level cache in size.

24. The method of claim 18, wherein said control unit maintains a program counter which is initialized to a starting address of said prefetch instructions in said buffer and is incremented by a preset amount until said counter equals an ending address of said prefetch instructions in said buffer.

25. The method of claim 24, further comprising the step of setting said select input flag bit to a first value indicating that said output is to equal said first input.

26. The method of claim 24, further comprising the steps of:

decoding a repeat instruction flag bit, said repeat instruction flag bit indicating that said prefetch instructions are to be placed into said buffer;

receiving a signal in said control unit, said signal indicating that said repeat instruction flag bit has been decoded;

re-initializing said program counter to said starting address; and

re-setting said select input flag bit to said first value.