Flash EEprom system

• US 6,684,345 B2
• Filed: 12/26/2002
• Issued: 01/27/2004
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): HUA, LY
• Application Number:
  US10/330,455
• Publication Number:
  US 20030097609A1
• Time in Patent Office: 397 Days
• Field of Search: 714/8, 714/723, 714/710, 365/185.16, 365/185.25, 365/185.02, 365/230.06
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A memory system, comprising:

non-volatile memory cells that are erasable and re-programmable, the memory cells being organized into units of memory cells that are erasable together,

a generator of an address of memory cells that is responsive to an address received by the memory system,

a data interface that passes data received by the memory system to the array for programming and that outputs data from the memory system that are read from the array,

a command sequencer,

the command sequencer being responsive to a read command received by the memory system to cause data to be read from a plurality of memory cells of the array in parallel by stepping through a predefined sequence of data read operations that include passing data read from the array and out of the memory system through the data interface, and

the command sequencer being responsive to a program command received by the memory system to cause data received by the memory system through the data interface to be programmed in parallel into multiple memory cells of the array by stepping through a predefined sequence of data programming operations including alternately programming and verifying a programmed state of the multiple memory cells.

2. The memory system of claim 1, wherein the memory cells are formed on more than one integrated circuit chip.

3. The memory system of claim 2, wherein the address generator, data interface and command sequencer are part of a controller of the memory system that is formed on an integrated circuit chip separate from the more than one integrated circuit chip containing the memory cells.

4. The memory system of claim 1, wherein the memory cells, the address generator, the data interface and the command sequencer are included in a single card having electrical contacts adapted to removably connect with a host system in order for the host to be able to communicate the read command, the program command and the received address to the memory system and to pass data between the host and the data interface of the memory system.

5. The memory system of claim 1, wherein the memory cells are characterized by being operated in more than two states in order to store more than one bit of data in individual memory cells.

6. A memory system, comprising:

an array of non-volatile memory cells that are erasable and re-programmable, the array being organized into units of memory cells that are erasable together,

an address generator including storage elements for storing a starting address within one of the erase units of memory cells in response to an address being received by the memory system,

a data interface including a buffer memory for passing data received by the memory system to the array for programming and for outputting data from the memory system that are read from the array,

a command sequencer,

the command sequencer being responsive to a read command received by the memory system to cause data to be read from multiple memory cells of the array in parallel, beginning with the starting address stored within the address generator, by stepping through a predefined sequence of data read operations that include passing data read from the array through an error correction circuit and out of the memory system through the data interface, and

the command sequencer being responsive to a program command received by the memory system to cause data received by the memory system through the data interface to be programmed in parallel into multiple memory cells of the array by stepping through a predefined sequence of data programming operations of the multiple memory cells.

7. The memory system of claim 6, wherein the address generator, data interface and command sequencer are part of a controller of the memory system formed on an integrated circuit chip separate from the memory array.

8. The memory system of claim 6, wherein the array of memory cells, the address generator, the data interface and the command sequencer are included in a single card having electrical contacts adapted to removably connect with a host system in order for the host to be able to communicate the read command and the program command to the memory system and to be able to pass data between the host and the data interface of the memory system.

9. A method of programming data into a memory system having an array of non-volatile re-programmable memory cells organized into a plurality of groups that individually contain a plurality of memory cells that are erasable together as a unit, comprising:

receiving an address from a host system and generating therefrom a corresponding address of memory cells within at least one of the groups of memory cells,

receiving the data to be programmed from the host system, and

in response to a programming command received from the host system by a command sequencer within the memory system, stepping through a sequence of programming operations predefined by the command sequencer to simultaneously program the received data into a plurality the addressed memory cells, the predefined sequence including repetitively programming and verifying the state of individual ones of the plurality of addressed memory cells until it is determined that the addressed memory cells have been programmed with the received data.

10. The method of claim 9, wherein the predefined sequence includes repetitively programming and verifying individual ones of the plurality of addressed memory cells into more than two states, whereby individual ones of the addressed memory cells are programmed to store more than one bit of the received data.

11. A method of reading data from a memory system having an array of non-volatile re-programmable memory cells organized into a plurality of groups that individually contain a plurality of memory cells that are erasable together as a unit, comprising:

receiving an address from a host system and generating therefrom a corresponding address of memory cells within at least one of the groups of memory cells,

in response to a read command received from the host system by a command sequencer within the memory system, stepping through a sequence of read operations predefined by the command sequencer to read data from the addressed memory cells, the predefined sequence including passing data read from the addressed memory cells through an error correction circuit, and

sending to the host system the data read from the addressed memory cells after passing through the error correction circuit.