Decompressor/PRPG for applying pseudo-random and deterministic test patterns

• US 6,684,358 B1
• Filed: 11/15/2000
• Issued: 01/27/2004
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US09/713,664
• Time in Patent Office: 1,168 Days
• Field of Search: 714/739, 714/733, 714/732, 714/728, 714/735, 714/738, 714/726, 714/736, 714/727, 324/158.1
• US Class Current: 714/739
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Claims

1. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising:

in a pseudo-random phase of operation;

providing an initial value;

generating from the initial value a set of pseudo-random test patterns; and

applying the pseudo-random test patterns to the scan chains in the circuit-under-test;

in a deterministic phase of operation;

providing a set of compressed deterministic test patterns;

decompressing a compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being provided; and

applying the decompressed deterministic test patterns to the scan chains in the circuit-under-test.

2. The method of claim 1 wherein the pseudo-random phase executes before the deterministic phase.

3. The method of claim 1 wherein the deterministic phase executes before the pseudo-random phase.

4. The method of claim 1 wherein the deterministic phase and the pseudo-random phase are executed at substantially the same time.

5. The method of claim 1 wherein the deterministic phase and the pseudo-random phase are executed at substantially different times.

6. The method of claim 1 wherein decompressing a compressed deterministic test pattern comprises generating one or more bits of a decompressed pattern by logically combining two or more bits of a compressed test pattern.

7. The method of claim 6 wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XOR operation.

8. The method of claim 6 wherein logically combining two or more bits of the compressed test pattern comprises combining the bits with an XNOR operation.

9. The method of claim 1 wherein the applying of a decompressed deterministic test pattern to scan chains of the circuit-under-test occurs as a compressed deterministic test pattern is being provided.

10. The method of claim 1 wherein providing a compressed test pattern comprises generating a serial stream of bits representing the compressed test pattern.

11. The method of claim 1 wherein providing a compressed test pattern comprises generating a parallel stream of bits representing the compressed test pattern.

12. The method of claim 1 including:

capturing in the scan chains the results of test pattern applications; and

comparing the results with a reference value.

13. The method of claim 1 wherein the compressed deterministic test pattern comprises a compressed partially specified test cube.

14. A system for applying test patterns to scan chains in a circuit-under-test comprising:

means for applying test patterns to the scan chains;

means for providing a set of compressed deterministic test patterns to the test pattern applying means;

means for providing an initial value to the test pattern applying means; and

means for configuring the test pattern applying means to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns from the initial value and to generate, in a deterministic phase of operation, a set of decompressed deterministic test patterns from the set of compressed deterministic test patterns.

15. The system of claim 14 including means for compressing responses to test patterns captured by the scan chains.

16. The system of claim 14 wherein the test pattern applying means includes a linear finite state machine.

17. The system of claim 14 wherein the test pattern applying means includes a phase shifter.

18. A circuit comprising:

a decompressor/PRPG;

control circuitry coupled to the decompressor/PRPG and operable to cause the decompressor/PRPG to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns and to generate, in a deterministic phase of operation, a set of decompressed deterministic test patterns from a set of provided compressed deterministic patterns;

circuit logic; and

scan chains coupled to the circuit logic and operable to receive test patterns generated by the decompressor/PRPG and to capture responses to the test patterns generated by the circuit logic,

wherein the decompressor/PRPG is operable to decompress a compressed deterministic test pattern as the compressed deterministic test pattern is being provided to the decompressor/PRPG.

19. The circuit of claim 18 wherein the decompressor/PRPG includes a linear finite state machine.

20. The circuit of claim 19 wherein the linear finite state machine includes a cellular automaton.

21. The circuit of claim 18 wherein the linear finite state machine includes a linear feedback shift register.

22. The circuit of claim 18 wherein the decompressor/PRPG includes a phase shifter.

23. The system of claim 22 wherein the phase shifter comprises an array of XOR gates.

24. The system of claim 22 wherein the phase shifter comprises an array of XNOR gates.

25. The circuit of claim 18 wherein the control circuitry is operable to provide an initial value to the decompressor/PRPG from which the decompressor/PRPG generates a set of pseudo-random test patterns.

26. The circuit of claim 25 wherein the control circuitry includes a BIST controller.

27. The circuit of claim 18 wherein the decompressor/PRPG is operable to receive from an external tester an initial value from which the decompressor/PRPG generates a set of pseudo-random test patterns.

28. The circuit of claim 18 wherein the control circuitry is operable to direct a set of compressed deterministic test patterns from an external tester to the decompressor/PRPG from which the decompressor/PRPG generates a set of decompressed deterministic test patterns.

29. The circuit of claim 28 wherein the control circuitry includes one or more logic gates through which the compressed deterministic patterns pass from the external tester to the decompressor/PRPG, the logic gates responsive to an enable signal.

30. The circuit of claim 18 wherein the decompressor/PRPG is operable to apply a decompressed deterministic test pattern to the scan chains as the compressed deterministic test pattern is being provided to the decompressor/PRPG.

31. The circuit of claim 18 including a multiple input signature register coupled to the scan chains and operable to compress responses to test patterns captured by the scan chains.

32. A circuit comprising:

means for applying test patterns to the scan chains;

means for configuring the test pattern applying means to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns and to generate, in a deterministic phase of operation, a set of deterministic test patterns;

circuit logic; and

scan chains coupled to the circuit logic and operable to receive test patterns generated by the test pattern applying means and to capture responses to the test patterns generated by the circuit logic.

33. The circuit of claim 32 including means for compressing responses to test patterns captured by the scan chains.

34. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising the following steps:

in a pseudo-random phase of operation;

a step for providing a initial value;

a step for generating from the initial value a set of pseudo-random test patterns; and

a step for applying the pseudo-random test patterns to the scan chains in the circuit-under-test;

in a deterministic phase of operation;

a step for providing a set of compressed deterministic test patterns;

a step for decompressing a compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being provided; and

a step for applying the deterministic test patterns to the scan chains in the circuit-under-test.

35. A method for applying test patterns to scan chains in a circuit-under-test, the method comprising the following steps:

a step for providing a set of compressed deterministic test patterns;

in a pseudo-random phase of operation;

a step for providing an initial value

a step for generating from the initial value a set of pseudo-random test patterns; and

a step for applying the pseudo-random test patterns to the scan chains in the circuit-under-test;

in a deterministic phase of operation;

a step for decompressing a compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being provided; and

a step for applying the deterministic test patterns to the scan chains in the circuit-under-test.

36. The method of claim 35, wherein the compressed deterministic test patterns comprise compressed partially specified test cubes.

37. The method of claim 35, wherein the deterministic test patterns have between 2% and 5% of bits deterministically specified.

38. The method of claim 35, where the providing a compressed deterministic test pattern step further comprises utilizing an automatic test pattern generation tool.

39. The method of claim 35, where the providing a compressed deterministic test pattern step further comprises determining at least one fault which is not detected by pseudo-random patterns, and then producing a partially specified test pattern based on the at least one fault.

40. The method of claim 39, further comprising compressing the partially specified test pattern to produce a compressed deterministic test pattern.

41. The method of claim 35, further comprising a step for providing uncompressed deterministic test patterns.