Semiconductor chip having both polycide and salicide gates and methods for making same

• US 6,686,276 B2
• Filed: 08/22/2002
• Issued: 02/03/2004
• Est. Priority Date: 03/09/2000
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Tower Semiconductor Limited
• Inventors: Aloni, Efraim, Edrei, Itzhak
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/226,487
• Publication Number:
  US 20030001220A1
• Time in Patent Office: 530 Days
• Field of Search: 438/275, 438/197, 438/199, 438/649, 438/651, 438/655, 438/682, 438/683
• US Class Current: 438/655
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.

Claims

1. A method of forming a semiconductor device comprising the steps of:

forming a polysilicon layer having a first portion and a second portion;

depositing a metal silicide layer on the first portion of the polysilicon layer, but not on the second portion of the polysilicon layer, whereby the first portion of the polysilicon layer becomes a polycide layer; and

depositing a metal layer over the second portion of the polysilicon layer.

2. The method of claim 1, further comprising the steps of:

etching the polycide layer to form one or more polycide gate electrodes; and

covering the polycide gate electrodes.

3. The method of claim 1, further comprising the steps of:

exposing the second portion of the polysilicon layer;

etching the exposed second portion of the polysilicon layer to define polysilicon gate electrode regions and expose source and drain regions; and

wherein the metal layer is deposited over the polysilicon gate electrode regions and the source and drain regions.

4. The method of claim 3, further comprising the step of causing the metal layer to react with the polysilicon gate electrode regions and the source/drain regions, thereby forming metal salicide regions.

5. The method of claim 1, further comprising the steps of:

forming a dielectric layer over the polysilicon layer, wherein the dielectric layer has a first portion overlying the first portion of the polysilicon layer and a second portion overlying the second portion of the polysilicon layer;

forming a photoresist mask over the second portion of the dielectric layer; and

removing the first portion of the dielectric layer.

6. The method of claim 1, further comprising the step of forming a dielectric layer over the polycide layer.

7. The method of claim 1, further comprising the step of forming one or more gate oxide layers.