Dropper-type DC stabilized power supply circuit provided with difference amplifiers for supplying a stable output voltage

• US 6,686,728 B2
• Filed: 05/28/2002
• Issued: 02/03/2004
• Est. Priority Date: 05/29/2001
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakajima, Akio
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US10/154,838
• Publication Number:
  US 20020180409A1
• Time in Patent Office: 616 Days
• Field of Search: 323/273, 323/274, 323/275, 323/280, 323/281
• US Class Current: 323/281
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A dropper-type DC stabilized power supply circuit is arranged such that a power transistor is connected in series with a power source line, a first difference amplifier compares (i) a feedback value acquired by dividing an output voltage with (ii) a reference voltage. The first difference amplifier controls the base current of the power transistor with reference to the difference above so as to stabilize the output voltage. This DC stabilized power supply circuit is additionally provided with second and third difference amplifiers having respective offset voltages in inputs thereof. When the output voltage surpasses a predetermined voltage level, the second difference amplifier restrains the base current. On the contrary, when the output voltage falls below a predetermined voltage level, the third difference amplifier increases a bias current of the first difference amplifier so as to increase the gain.

Claims

1. A DC stabilized power supply circuit, comprising:

a power transistor connected in series with a power supply line;

a first difference amplifier in which an output voltage is stabilized by controlling a base current of said power transistor according to a difference between a feedback value of said output voltage and a predetermined first internal reference voltage so that said feedback value and said first internal reference voltage are equal to each other;

a second difference amplifier in which a second internal reference voltage greater than said first internal reference voltage by a predetermined level is set, and the greater said feedback value of the output voltage is than said second internal reference voltage, the more said base current of the power transistor is restrained; and

a third difference amplifier in which a third internal reference voltage smaller than said first internal reference voltage by a predetermined level is set, and the smaller said feedback value of the output voltage is than said third internal reference voltage, the more a gain of said first difference amplifier is increased.

2. The DC stabilized power supply circuit as defined in claim 1, wherein said second and third difference amplifiers respectively generate said second internal reference voltage which is greater than said first internal reference voltage by the predetermined level and said third internal reference voltage which is smaller than said first internal reference voltage by the predetermined level respectively, using band gap voltages due to differences (i) between an emitter area ratio of a differential pair of said first difference amplifier and an emitter area ratio of a differential pair of said second difference amplifier and (ii) between said emitter area ratio of said differential pair of said first difference amplifier and an emitter area ratio of a differential pair of said third difference amplifier, respectively.

3. The DC stabilized power supply circuit as defined in claim 1, wherein:

said first difference amplifier detects said difference between said feedback value and said first internal reference voltage, according to said feedback value supplied to the first difference amplifier and the external reference voltage supplied to the first difference amplifier;

said second difference amplifier includes a differential pair composed of two transistors each having different emitter area, wherein a base of one of said two transistors receives said feedback value of the output voltage and a base of the other of said transistors receives said external reference voltage;

said third difference amplifier includes a differential pair composed of two transistors each having different emitter area, wherein a base of one of said transistors receives said feedback value of the output voltage and a base of the other of said transistors receives said external reference voltage; and

said emitter area of each of said transistors is arranged, in accordance with a band gap voltage of each of said differential pairs so as to make (i) said second internal reference voltage greater than said first internal reference voltage by said predetermined level and (ii) said third internal reference voltage smaller than said first internal reference voltage by said predetermined level.

4. The DC stabilized power supply circuit as defined in claim 1, further comprising a bypass transistor provided between a base and an emitter of said power transistor, wherein said second difference amplifier causes said bypass transistor to supply a current to a path of said base current so as to restrain said base current of the power transistor.

5. The DC stabilized power supply circuit as defined in claim 1, wherein said third difference amplifier increases a constant current flown through the differential pair of said first difference amplifier so as to increase a gain of said first difference amplifier.

6. The DC stabilized power supply circuit as define in claim 1, wherein the first internal reference voltage corresponds to the external reference voltage, the second internal reference voltage is set as the external reference voltage plus the offset voltage of the second difference amplifier, and the third internal reference voltage is set as the external reference voltage minus the offset voltage of the third difference amplifier.

7. The DC stabilized power supply circuit as defined in claim 1, wherein the first, second, and third internal reference voltages are set based on a relationship between an external reference voltage and offset voltages generated due to variations of emitter areas in the first, second, and third difference amplifiers, respectively.