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Techniques for testing embedded cores in multi-core integrated circuit designs

  • US 6,686,759 B1
  • Filed: 11/28/2000
  • Issued: 02/03/2004
  • Est. Priority Date: 11/28/2000
  • Status: Active Grant
First Claim
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1. A circuit for facilitating the testing of an integrated circuit that is comprised of multiple circuit blocks, each of the circuit blocks including a test access port, the circuit comprising:

  • a demultiplexer connected to a chip-level test input signal, said demultiplexer having a plurality of outputs connected to said circuit blocks;

    a multiplexer connected to a chip-level test output signal, said multiplexer having a plurality of inputs received from said circuit blocks; and

    a select register connected to said demultiplexer and to said multiplexer, said select register routing the input of said demultiplexer to the output of said demultiplexer and the input of said multiplexer to the output of said multiplexer according to a plurality of bits loaded into the select register.

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