High-speed fully balanced differential flip-flop with reset

• US 6,686,787 B2
• Filed: 02/28/2002
• Issued: 02/03/2004
• Est. Priority Date: 02/28/2002
• Status: Expired due to Fees

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Ling, Kuok
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): NGUYEN, LONG T
• Application Number:
  US10/090,593
• Publication Number:
  US 20030160644A1
• Time in Patent Office: 705 Days
• Field of Search: 327/202, 327/203, 327/208, 327/210, 327/211-215, 327/217-219, 327/57
• US Class Current: 327/203
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a differential reset circuit. The clock circuit having complementary clock inputs to alternately set and store data in the data set and data store circuits. The differential reset circuit ties to the differential output and is operative in response to a reset signal to force the differential output to a predetermined logic level. The differential reset circuit includes matched complementary reset drivers to exhibit like capacitances. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell.

Claims

1. A differential flip-flop including:

a master cell comprising

a first data set circuit having a first differential input and a first differential output,

a first data store circuit coupled to the output, of the first data set circuit,

a differential clock circuit having complementary clock inputs to alternately set and store data in the first data set and first data store circuits, and

a differential reset circuit tied to the differential output and operative in response to a reset signal to force the differential output to a predetermined logic level, the differential reset circuit including matched complementary reset driver circuitry; and

a slave cell formed substantially similar to the master cell, the slave cell having a second differential input coupled to the first differential output of the master cell.

2. A differential flip-flop according to claim 1 wherein:

the matched complementary reset driver circuitry includes a reset driver path and a reset complement driver path, both paths having matched capacitances.

3. A differential flip-flop according to claim 2 wherein:

the reset driver and complementary driver paths each include a single driver.

4. A differential flip-flop according to claim 3 wherein:

each single driver comprises a single transistor.

5. A differential flip-flop according to claim 1 wherein:

the matched complementary reset driver circuitry comprises circuits operating at matching parameters.

6. A differential flip-flop according to claim 1 wherein:

the matched complementary reset driver circuitry comprises transistors having matched sizes.

7. A differential flip-flop according to claim 1 wherein:

the differential reset circuit includes an input responsive to a logic signal, and an output directly coupled to the differential output.

8. A differential flip-flop according to claim 1 wherein:

each of the matched complementary reset drivers comprises a single transistor.