High resolution, high speed, low power switched capacitor analog to digital converter

• US 6,686,865 B2
• Filed: 06/06/2003
• Issued: 02/03/2004
• Est. Priority Date: 04/01/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Confalonieri, Pierangelo, Zamprogno, Marco, Nagari, Angelo
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US10/455,894
• Publication Number:
  US 20030197636A1
• Time in Patent Office: 242 Days
• Field of Search: 341/172, 341/150, 341/118, 341/144, 341/145, 341/120, 341/155, 341/156
• US Class Current: 341/172
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, C_s and C_ATT respectively, that substantially satisfy the relationship: (2^p−1)·C_s−C_ATT=2^p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.

Claims

1. An analog to digital converter for converting an analog input voltage to a digital output voltage, comprising:

a first converter segment having a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of said capacitors having a first electrode connected to a first common node and a second electrode connected through respective controllable switching means to either one of a first reference voltage terminal and an input terminal at which the input voltage is received;

a second converter segment having a second array of binary weighted capacitors with respective capacitances that are integer multiples of said predetermined unit capacitance, each of the capacitors of the second converter segment having a first electrode connected to a second common node and a second electrode connected through respective controllable switching means to either one of said first reference voltage terminal and said input terminal;

a coupling capacitor with a first electrode connected to the first common node and a second electrode connected to the second common node;

a comparator having a first input coupled to the second common node, a second input coupled to a reference voltage, and an output;

control means coupled to the controllable switching means of the first and second converter segments to open or close selectively the controllable switching means and for producing the digital output signal based on a signal received from the comparator; and

capacitance means connected between the first common node and a reference voltage terminal, wherein the coupling capacitor and the capacitance means have capacitances, C_s and C_ATT respectively, that substantially satisfy a relationship;

(2^p−

1)·

C_s−

C_ATT=2^p·

C, where p is a number of bits coded in the first converter segment and C is the unit capacitance.

2. The converter of claim 1 wherein the capacitance means includes first, second, and third capacitors, the first and second capacitors being coupled between the first common node and the reference voltage terminal and the third capacitor being coupled between the first common node and the input terminal.

3. The converter of claim 2 wherein the capacitance means further includes a first switch coupled between the first capacitor and the reference voltage terminal and a second switch coupled between the third capacitor and the reference voltage terminal, the converter further comprising a bit register having first and second control outputs respectively coupled to respective control terminals of the first and second switches.

4. The converter of claim 1 wherein a capacitor with a smallest capacitance in the first converter segment has substantially a same capacitance as a capacitor with a smallest capacitance in the second converter segment.

5. The converter of claim 1 wherein the capacitance means comprises at least one capacitor having a first electrode connected to the first common node and a second electrode connected, through associated controllable switching means, to either one of said reference voltage terminal and said input terminal, and the control means are coupled to the controllable switching means associated with said at least one capacitor to open or close the connection to the reference voltage terminal and said input terminal.

6. An analog to digital converter to convert an analog input signal to a digital output signal, the converter comprising:

a first converter segment having a first array of binary weighted capacitors with respective capacitances that are integer multiples of a predetermined unit capacitance, each of said capacitors having a first electrode coupled to a first common node and a second electrode coupled through respective controllable switches to either one of a first reference voltage terminal and an input terminal at which the input signal is to be received;

a second converter segment having a second array of binary weighted capacitors with respective capacitances that are integer multiples of said predetermined unit capacitance, each of the capacitors of the second converter segment having a first electrode coupled to a second common node and a second electrode coupled through respective controllable switches to either one of said first reference voltage terminal and said input terminal;

a coupling capacitor with a first electrode coupled to the first common node and a second electrode coupled to the second common node;

a comparator having a first terminal coupled to the second common node, a second terminal coupled to a second reference voltage terminal, and third terminal;

a control unit coupled to the controllable switches of the first and second converter segments to selectively open or close the controllable switches and to produce the digital output signal based on a signal received from the third terminal of the comparator; and

a capacitance element permanently connected between the first common node and a third reference voltage terminal, wherein the coupling capacitor and the capacitance element have capacitances, C_s and C_ATT respectively, that substantially satisfy a relationship;

(2^p−

1)·

C_s−

C_ATT=2^p·

C, where p is a number of bits coded in the first converter segment and C is the unit capacitance.

7. The converter of claim 6 wherein the capacitance element includes first, second, and third capacitors, the first and third capacitors being coupled between the first common node and either one of the first reference voltage terminal and the input terminal, and the second capacitor being coupled between the first common node and the third voltage reference terminal.

8. The converter of claim 7 further including:

a first switch coupled between the first capacitor and the first reference voltage terminal;

a second switch coupled between the third capacitor and the first reference voltage terminal; and

a bit register having first and second control output terminals respectively coupled to respective control terminals of the first and second switches.

9. The converter of claim 6 wherein a capacitor with a smallest capacitance in the first converter segment has substantially a same capacitance as a capacitor with a smallest capacitance in the second converter segment.

10. The converter of claim 6 wherein the capacitance element includes at least one capacitor having a first electrode coupled to the first common node and a second electrode coupled, through associated controllable switches, to either one of said first reference voltage terminal and said input terminal, and wherein the control unit is coupled to the controllable switches associated with said at least one capacitor to open or close connection to the first reference voltage terminal and said input terminal.

11. The converter of claim 6 wherein the second voltage reference terminal comprises a ground terminal.

12. The converter of claim 6 wherein the third voltage reference terminal comprises a ground terminal.