Preview mode low resolution output system and method

• US 6,686,957 B1
• Filed: 03/31/1999
• Issued: 02/03/2004
• Est. Priority Date: 03/31/1999
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Johnson, Sandra M., Holberg, Douglas R., Itani, Nadi R.
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): Villecco, John M
• Application Number:
  US09/282,524
• Time in Patent Office: 1,770 Days
• Field of Search: 348/220.1, 348/221.1, 348/222.1, 348/229.1, 348/230.1, 348/254, 348/255, 348/333.11, 348/333.13, 348/372, 341/139, 341/161, 341/162, 341/155
• US Class Current: 348/222.1
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/007 among different resolutions
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04N 23/667 Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
• CPC Class Codes: H04N 23/84 for processing colour signals

Abstract

A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.

Claims

1. A processing system for an imager device comprising:

a camera system for producing an imager signal;

a correlated double sample (CDS) circuit for receiving data from an imager;

a variable gain amplifier (VGA) circuit configured to be selectably settable at one of a plurality of predetermined data resolution levels wherein one of the predetermined data resolution levels is a reduced data resolution level;

a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit; and

a gain adjust circuit coupled to said ADC, said gain adjust circuit configured to produce an output signal of selected magnitude.

2. A processing system according to claim 1 wherein said VGA includes at least a single amplifier which is settable between first and second predetermined current levels.

3. The proceeding system according 2 wherein one of the first and second predetermined current levels is a reduced drive current level.

4. The processing system according to claim 3 wherein the VGA selectably set to the reduced drive current level produces a preview digital image.

5. A method for processing image signals, comprising:

producing an image signal;

amplifying said image signals at a selected one of first and second drive current levels;

converting said image signals into digital signals having a selected one of first and second data solution levels; and

selecting a reduced drive current level to produce a preview digital image.

6. The method according to claim 5 including selecting a high drive current level to produce an enhanced digital image.

7. The method according to claim 6 wherein said enhanced digital image is a still image.

8. The method according to claim 5 wherein said preview digital image is a video image.

9. A processing system for an imager device comprising:

a camera system for producing an imager signal;

a correlated double sample (CDS) circuit for receiving data from an imager;

a variable gain amplifier (VGA) circuit configured to be selectably settable at one of a plurality of predetermined data resolution levels wherein one of the predetermined data resolution levels is a reduced data resolution level;

a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit;

a gain adjust circuit coupled to said ADC, said gain adjust circuit configured to produce an output signal of selected magnitude; and

a compander coupled to said gain adjust circuit for reducing the bit-width of the output signal produced by said gain adjust circuit.

10. The processing system according to claim 9 wherein said VGA includes at least a single amplifier which is settable between first and second predetermined current levels.

11. The processing system, according to claim 10 wherein one of the first and second predetermined current levels is a reduced drive current level.

12. The processing system according to claim 11 wherein the VGA selectably set to the reduced drive current level produces a preview digital image.

13. A method for processing image signals, comprising:

producing an image signal;

amplifying said image signals at a selected one of first and second drive current levels wherein one of said first and second drive current levels is a reduced drive current level; and

converting said image signals into digital signals having a selected one of first and second data resolution levels wherein one of said first and second data resolution levels is a reduced data resolution level.

14. The method according to claim 13 further comprising:

selecting the reduced drive current level to produce a preview digital image at the reduced data resolution level.