AC to DC inverter for use with AC synchronous motors

• US 6,687,142 B2
• Filed: 12/17/2001
• Issued: 02/03/2004
• Est. Priority Date: 12/17/2001
• Status: Expired due to Fees

• Current Assignee: CoolIT Systems Inc.
• Original Assignee: CoolIT Systems Inc.
• Inventors: Scott, Robert John Charles
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US10/016,678
• Publication Number:
  US 20030112646A1
• Time in Patent Office: 778 Days
• Field of Search: 363/97, 363/98, 363/131, 363/132, 363/134, 363/56.04, 363/56.07
• US Class Current: 363/97
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 7/53871 with automatic control of output voltage or current

Abstract

AC to DC inverters that are formed from electronic switches, such as MOSFETs, that are controlled by gating pulses obtained from comparators. The comparators compare a varying signal against two closely spaced reference voltages so as to provide gating pulses with delays needed to prevent shoot-through in the electronic switches.

Claims

1. An electronic circuit for driving an AC synchronous motor having a center-tapped winding from a DC supply current, comprising:

a first DC input terminal and a second DC input terminal, the first DC input terminal for connection to the DC supply current at a more positive voltage than the second DC input terminal;

three output terminals for connection to the motor winding, the first and third output terminals for connection to the respective end taps of the motor winding and the second output terminal for connection to the center tap of the motor winding;

a resistive voltage ladder connected between the first DC input terminal and the second DC input terminal, the resistive voltage ladder providing a first reference voltage and a second reference voltage, the first reference voltage more positive than the second reference voltage when the first DC input terminal and second DC input terminal are connected to the DC supply current;

a DC-offset reference voltage between the first reference voltage and the second reference voltage provided by the resistive voltage ladder;

a signal generator connected to the resistive voltage ladder so as to provide a reference signal varying between a maximum voltage that is more positive than the first reference voltage and a minimum voltage that is less positive than the second reference voltage, the reference signal having a preselected waveform so that the reference signal crosses a voltage range between the reference voltages in a preselected time and remains more positive than the first reference voltage for approximately the same time that it remains below the second reference voltage;

a voltage follower connected between the resistive voltage ladder and the signal generator so as to provide the DC-offset reference voltage to the signal generator;

a first comparator/buffer connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the first reference voltage and provide as an output a first series of positive-going output pulses each lasting during the time that the reference signal is more positive than the first reference voltage;

a second comparator/buffer connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the second reference voltage and provide as an output a second series of positive-going output pulses each lasting during the time that the reference signal is less positive than the second reference voltage;

a first N-channel MOSFET switch having a gate connected to the output of the first comparator/buffer, a drain connected to the first output terminal, and a source connected to the second DC input terminal, the drain and source are connected together while an output pulse is applied to the gate; and

a second N-channel MOSFET switch having a gate connected to the output of the second comparator/buffer, a drain connected to the third output terminal, and a source connected to the second DC input terminal, the drain and source are connected together while an output pulse is applied to the gate.

2. The electronic circuit as defined in claim 1, wherein:

the signal generator comprises an operational amplifier configured as a relaxation oscillator so that the time-varying signal has a generally triangular waveform;

the voltage follower comprises an operational amplifier; and

the comparator/buffers comprise operational amplifiers.

3. A DC to AC inverter for providing an AC output current from a DC supply current, comprising:

a first DC input terminal and a second DC input terminal, the first DC input terminal for connection to the DC supply current at a more positive voltage than the second DC input terminal;

first and second output terminals for connection to a device requiring the AC output current;

a resistive voltage ladder connected between the first DC input terminal and the second DC input terminal for providing a first reference voltage and a second reference voltage, the first reference voltage more positive than the second reference voltage;

a DC-offset reference voltage between the first reference voltage and the second reference voltage provided by the resistive voltage ladder;

a signal generator for generating a reference signal that varies between a maximum voltage that is more positive than the first reference voltage and a minimum voltage that is less positive than the second reference voltage, the reference signal having a preselected waveform so that the reference signal crosses a voltage range between the reference voltages in a preselected time and remains more positive than the first reference voltage for approximately the same time that it remains below the second reference voltage;

a voltage follower connected between the resistive voltage ladder and the signal generator so as to provide the DC-offset reference voltage to the signal generator;

a first comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the first reference voltage and provide as an output a first series of output pulses that are positive-going each lasting during the time that the reference signal is less positive than the first reference voltage;

a second comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the second reference voltage and provide as an output a second series of output pulses that are positive-going each lasting during the time that the reference signal is less positive than the second reference voltage;

a third comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the second reference voltage and provide as an output a third series of output pulses that are positive-going each lasting during the time that the reference signal is more positive than the second reference voltage;

a fourth comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the first reference voltage and provide as an output a fourth series of output pulses that are positive-going each lasting during the time that the reference signal is more positive than the first reference voltage;

a first P-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first comparator, the drain is connected to the first DC input terminal, and the source is connected to the first output terminal;

a second N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second comparator, the drain is connected to the first output terminal, and the source is connected to the second DC input terminal;

a third P-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the third comparator, the drain is connected to the first DC input terminal, and the source is connected to the second output terminal; and

a fourth N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the fourth comparator, the drain is connected to the second output terminal, and the source is connected to the second DC input terminal.

4. The electronic circuit as defined in claim 3, wherein:

the signal generator comprises an operational amplifier configured as a relaxation oscillator so that the time-varying signal has a generally triangular waveform;

the voltage follower comprises an operational amplifier; and

the comparators comprise operational amplifiers.

5. A DC to AC inverter for providing an AC output current from a DC supply current, comprising:

a first DC input terminal and a second DC input terminal, the first DC input terminal for connection to the DC supply current at a more positive voltage than the second DC input terminal;

first and second output terminals for connection to a device requiring the AC output current;

a resistive voltage ladder connected between the first DC input terminal and the second DC input terminal, the resistive voltage ladder providing a first reference voltage and a second reference voltage, the first reference voltage more positive than the second reference voltage;

a DC-offset reference voltage between the first reference voltage and the second reference voltage provided by the resistive voltage ladder;

a signal generator for generating a reference signal that varies between a maximum voltage that is more positive than the first reference voltage and a minimum voltage that is less positive than the second reference voltage, the reference signal having a preselected waveform so that the reference signal crosses a voltage range between the reference voltages in a preselected time and remains more positive than the first reference voltage for approximately the same time that it remains below the second reference voltage;

a voltage follower connected between the resistive voltage ladder and the signal generator so as to provide the DC-offset reference voltage to the signal generator;

a first comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the first reference voltage and provide as an output a first series of output pulses that are positive-going each lasting during the time that the reference signal is more positive than the first reference voltage;

a second comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the second reference voltage and provide as an output a second series of output pulses that are positive-going each lasting during the time that the reference signal is less positive than the second reference voltage;

a first buffer connected to the output of the first comparator so as to buffer the first comparator and provide the first series of positive-going output pulses at its output;

a first buffer/inverter connected to the output of the first comparator so as to buffer the first comparator and provide a series of zero-going output pulses that are the inverse of the first series of positive-going output pulses at its output;

a second buffer connected to the output of the second comparator so as to buffer the second comparator and provide the second series of positive-going output pulses at its output;

a second buffer/inverter connected to the output of the second comparator so as to buffer the second comparator and provide a series of zero-going output pulses that are the inverse of the second series of positive-going output pulses at its output;

a first P-channel MOSFET switch having a gate, a drain, and source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer/inverter, the drain is connected to the first DC input terminal, and the source is connected to the first output terminal;

a second N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer, the drain is connected to the first output terminal, and the source is connected to the second DC input terminal;

a third P-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer/inverter, the drain is connected to the first DC input terminal, and the source is connected to the second output terminal; and

a fourth N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer, the drain is connected to the second output terminal, and the source is connected to the second DC input terminal.

6. The electronic circuit as defined in claim 5, wherein:

the signal generator comprises an operational amplifier configured as a relaxation oscillator so that the time-varying signal has a generally triangular waveform;

the voltage follower comprises an operational amplifier;

the comparators comprise operational amplifiers; and

the buffers and buffer/inverters comprise operational amplifiers.

7. A DC to AC inverter for providing an AC output current from a DC supply current, comprising:

a first DC input terminal and a second DC input terminal, the first DC input terminal for connection to the DC supply current at a more positive voltage than the second DC input terminal;

first and second output terminals for connection to a device requiring the AC output current;

a resistive voltage ladder connected between the first DC input terminal and the second DC input terminal, the resistive voltage ladder providing a first reference voltage and a second reference voltage, the first reference voltage more positive than the second reference voltage;

a DC-offset reference voltage between the first reference voltage and the second reference voltage provided by the resistive voltage ladder;

a signal generator for generating a reference signal that varies between a maximum voltage that is more positive than the first reference voltage and a minimum voltage that is less positive than the second reference voltage, the reference signal having a preselected waveform so that the reference signal crosses a voltage range between the reference voltages in a preselected time and remains more positive than the first reference voltage for approximately the same time that it remains below the second reference voltage;

a voltage follower connected between the resistive voltage ladder and the signal generator so as to provide the DC-offset reference voltage to the signal generator;

a first comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the first reference voltage and provide as an output a first series of output pulses that are positive-going each lasting during the time that the reference signal is more positive than the first reference voltage;

a second comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the second reference voltage and provide as an output a second series of output pulses that are positive-going each lasting during the time that the reference signal is less positive than the second reference voltage;

a first buffer connected to the output of the first comparator so as to buffer the first comparator and provide the first series of positive-going output pulses at its output;

a first buffer/inverter connected to the output of the first comparator so as to buffer the first comparator and provide a series of zero-going output pulses that are the inverse of the first series of positive-going output pulses at its output;

a second buffer connected to the output of the second comparator so as to buffer the second comparator and provide the second series of positive-going output pulses at its output;

a second buffer/inverter connected to the output of the second comparator so as to buffer the second comparator and provide a series of zero-going output pulses that are the inverse of the second series of positive-going output pulses at its output;

a first P-channel MOSFET switch having a gate, a drain, and source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer, the drain is connected to the first DC input terminal, and the source is connected to the first output terminal;

a second N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer, the drain is connected to the first output terminal, and the source is connected to the second DC input terminal;

a third P-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer/inverter, the drain is connected to the second DC input terminal, and the source is connected to the second output terminal; and

a fourth N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer/inverter, the drain is connected to the second output terminal, and the source is connected to the second DC input terminal.

8. The electronic circuit as defined in claim 7, wherein:

the signal generator comprises an operational amplifier configured as a relaxation oscillator so that the time-varying signal has a generally triangular waveform;

the voltage follower comprises an operational amplifier;

the comparators comprise operational amplifiers; and

the buffers and buffer/inverters comprise operational amplifiers.

9. A DC to AC inverter for providing an AC output current from a DC supply current, comprising:

a first DC input terminal and a second DC input terminal, the first DC input terminal for connection to the DC supply current at a more positive voltage than the second DC input terminal;

first and second output terminals for connection to a device requiring the AC output current;

a resistive voltage ladder connected between the first DC input terminal and the second DC input terminal, the resistive voltage ladder providing a first reference voltage and a second reference voltage, the first reference voltage more positive than the second reference voltage;

a DC-offset reference voltage between the first reference voltage and the second reference voltage provided by the resistive voltage ladder;

a signal generator for generating a reference signal that varies between a maximum voltage that is more positive than the first reference voltage and a minimum voltage that is less positive than the second reference voltage, the reference signal having a preselected waveform so that the reference signal crosses a voltage range between the reference voltages in a preselected time and remains more positive than the first reference voltage for approximately the same time that it remains below the second reference voltage;

a voltage follower connected between the resistive voltage ladder and the signal generator so as to provide the DC-offset reference voltage to the signal generator;

a first comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the first reference voltage and provide as an output a first series of output pulses that are positive-going each lasting during the time that the reference signal is less positive than the first reference voltage;

a second comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the second reference voltage and provide as an output a second series of output pulses that are positive-going each lasting during the time that the reference signal is less positive than the second reference voltage;

a first buffer connected to the output of the first comparator so as to buffer the first comparator and provide the first series of positive-going output pulses at its output;

a first buffer/inverter connected to the output of the first comparator so as to buffer the first comparator and provide a series of zero-going output pulses that are the inverse of the first series of positive-going output pulses at its output;

a second buffer connected to the output of the second comparator so as to buffer the second comparator and provide the second series of positive-going output pulses at its output;

a second buffer/inverter connected to the output of the second comparator so as to buffer the second comparator and provide a series of zero-going output pulses that are the inverse of the second series of positive-going output pulses at its output;

a first P-channel MOSFET switch having a gate, a drain, and source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer/inverter, the drain is connected to the first DC input terminal, and the source is connected to the first output terminal;

a second N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer/inverter, the drain is connected to the first output terminal, and the source is connected to the second DC input terminal;

a third P-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer, the drain is connected to the second DC input terminal, and the source is connected to the second output terminal; and

a fourth N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer, the drain is connected to the second output terminal, and the source is connected to the second DC input terminal.

10. The electronic circuit as defined in claim 9, wherein:

the signal generator comprises an operational amplifier configured as a relaxation oscillator so that the time-varying signal has a generally triangular waveform;

the voltage follower comprises an operational amplifier;

the comparators comprise operational amplifiers; and

the buffers and buffer/inverters comprise operational amplifiers.

11. A DC to AC inverter for providing an AC output current from a DC supply current, comprising:

a first DC input terminal and a second DC input terminal, the first DC input terminal for connection to the DC supply current at a more positive voltage than the second DC input terminal;

first and second output terminals for connection to a device requiring the AC output current;

a resistive voltage ladder connected between the first DC input terminal and the second input terminal, the resistive voltage ladder providing a first reference voltage and a second reference voltage, the first reference voltage more positive than the second reference voltage;

a DC-offset reference voltage between the first reference voltage and the second reference voltage provided by the resistive voltage ladder;

a signal generator for generating a reference signal that varies between a maximum voltage that is more positive than the first reference voltage and a minimum voltage that is less positive than the second reference voltage, the reference signal having a preselected waveform so that the reference signal crosses a voltage range between the reference voltages in a preselected time and remains more positive than the first reference voltage for approximately the same time that it remains below the second reference voltage;

a voltage follower connected between the resistive voltage ladder and the signal generator so as to provide the DC-offset reference voltage to the signal generator;

a first comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the first reference voltage and provide as an output a first series of output pulses that are positive-going each lasting during the time that the reference signal is less positive than the first reference voltage;

a second comparator connected to the signal generator and the resistive voltage ladder so as to compare the reference signal to the second reference voltage and provide as an output a second series of output pulses that are positive-going each lasting during the time that the reference signal is more positive than the second reference voltage;

a first buffer connected to the output of the first comparator so as to buffer the first comparator and provide the first series of positive-going output pulses at its output;

a first buffer/inverter connected to the output of the first comparator so as to buffer the first comparator and provide a series of zero-going output pulses that are the inverse of the first series of positive-going output pulses at its output;

a second buffer connected to the output of the second comparator so as to buffer the second comparator and provide the second series of positive-going output pulses at its output;

a second buffer/inverter connected to the output of the second comparator so as to buffer the second comparator and provide a series of zero-going output pulses that are the inverse of the second series of positive-going output pulses at its output;

a first P-channel MOSFET switch having a gate, a drain, and source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer, the drain is connected to the first DC input terminal, and the source is connected to the first output terminal;

a second N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer/inverter, the drain is connected to the first output terminal, and the source is connected to the second DC input terminal;

a third P-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the first buffer, the drain is connected to the second DC input terminal, and the source is connected to the second output terminal; and

a fourth N-channel MOSFET switch having a gate, a drain, and a source, the drain and source are connected together while an output pulse is applied to the gate, the gate is connected to the output of the second buffer/inverter, the drain is connected to the second output terminal, and the source is connected to the second DC input terminal.

12. The electronic circuit as defined in claim 11, wherein:

the signal generator comprises an operational amplifier configured as a relaxation oscillator so that the time-varying signal has a generally triangular waveform;

the voltage follower comprises an operational amplifier;

the comparators comprise operational amplifiers; and

the buffers and buffer/inverters comprise operational amplifiers.