Cubic memory array with diagonal select lines

• US 6,687,147 B2
• Filed: 07/23/2002
• Issued: 02/03/2004
• Est. Priority Date: 04/02/2002
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter, Koll, Andrew
• Primary Examiner(s): Nguyen, Van Thu
• Assistant Examiner(s): HUR, JUNG H
• Application Number:
  US10/202,174
• Publication Number:
  US 20030185049A1
• Time in Patent Office: 560 Days
• Field of Search: 365/51, 365/67, 365/63, 365/130
• US Class Current: 365/63
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.

Claims

1. A cubic memory array, comprising:

a plurality of memory cells arranged in arrays with rows and columns, said arrays being layered on a substrate;

a plurality of conductive pillars, each conductive pillar being connected to a plurality of said memory cells and extending between layers of memory cells;

a first plurality of select lines that are each connected to a plurality of said memory cells in a row; and

a second plurality of select lines that are each connected to a plurality of said conductive pillars and are divided into first and second groups;

wherein said first group is arranged diagonally among said conductive pillars.

2. The cubic memory array of claim 1, wherein each of said second plurality of select lines is connected to every other pillar along a length of that select line.

3. The cubic memory array of claim 1, further comprising control circuitry formed around a periphery of said cubic memory array, said control circuit selectively effecting reading and writing of data to said memory cells.

4. The cubic memory array of claim 3, wherein said control circuitry comprises a switching element electrically connected to at least one pillar.

5. The cubic memory array of claim 3, wherein a single switching element in said control circuitry simultaneously accesses and controls a plurality of select lines from both said first and second pluralities of select lines.

6. The cubic memory array of claim 3, wherein said control circuitry may simultaneously drive a plurality of said pillars that are connected to different select lines.

7. The cubic memory array of claim 1, wherein a first layer of said memory cells is formed directly on a surface of said substrate.

8. The cubic memory array of claim 1, further comprising circuitry formed on said substrate under said memory cells, pillars and select lines of said cubic memory array.

9. The cubic memory array of claim 1, wherein select lines of said first group are arranged diagonally at a 45 degree angle with respect to said rows and columns of said memory cells.

10. A method of creating a memory circuit, comprising:

forming a first plurality of select-lines in a plane substantially parallel to a substrate;

forming a second plurality of select-lines in a plane substantially parallel to said substrate, said second plurality of select-lines being divided into first and second groups, wherein said first group is formed in a direction normal to that of said first plurality of select-lines, and said second group is formed in a direction substantially diagonal to that of said first group;

forming a plurality of pillars normal to said substrate; and

forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.

11. The method of claim 10, further comprising electrically connecting each of said second plurality of select lines to every other pillar along a length of that select line.

12. The method of claim 10, further comprising forming another layer of memory cells, disposed in an array, on said array of memory cells.

13. The method of claim 10, further comprising forming control circuitry around a periphery of said cubic memory array, said control circuit selectively effecting reading and writing of data to said memory cells.

14. The method of claim 13, wherein said forming said control circuitry comprises forming a switching element electrically connected to at least one pillar.

15. The method of claim 10, further forming circuitry on said substrate under said memory cells, pillars and select lines of said cubic memory array.

16. The method of claim 10, further comprising forming said memory circuit on an existing circuit formed on said substrate.

17. The method of claim 10, further comprising forming a first layer of said memory cells directly on a surface of said substrate.

18. A cubic memory array, comprising:

storage means for storing digital data; and

control means for reading and writing digital data in said storage means, said control means comprising a plurality of selection lines connected to memory cells in said storage means; and

means for reducing cross-coupling between said selection lines.

19. The cubic memory array of claim 18, said control means further comprise a plurality of conductive pillars connected to said selection lines and said memory cells.

20. The cubic memory array of claim 19, wherein said means for reducing cross-coupling between said selection lines comprises disposing a first group of said selection lines above said conductive pillars and disposing a second group of said selection lines below said conductive pillars.

21. The cubic memory array of claim 18, said control means further comprise means for controlling a plurality of said selection lines with a single control element.

22. The cubic memory array of claim 18, wherein said control means access a plurality of said memory cells simultaneously.

23. The cubic memory array of claim 18, wherein said means for reducing cross-coupling between said selection lines comprises disposing a first group of said selection lines diagonal to a second group of said selection lines.